Micron preps embedded DRAM for SoC push

Micron preps embedded DRAM for SoC push
By Anthony Cataldo, EE Times
October 11, 2000 (5:27 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001011S0026

SAN JOSE, Calif. — In yet another attempt to remake itself as something other than a commodity DRAM maker, Micron Technology Inc. plans to ply a new embedded DRAM technology and a MIPS processor license to build application-specific devices for use by customers inside and outside of Micron.

That strategy was partly spelled out here at the Microprocessor Forum, where vice president of integrated products Dean Klein described the company's 0.15-micron embedded DRAM technology that should be finalized for production by year's end.

And Wednesday (Oct. 11), the company announced it has licensed the 32-bit 4-Kc and 64-bit 5-Kc synthesizable cores from MIPS Technologies Inc. Micron plans to combine the MIPS cores with its homegrown embedded DRAM process technology for system-on-chip solutions targeting a number of applications such as graphics, set-top boxes, voice recognition systems, PC peripherals, communications, consumer devices and network ing, Klein said. Other than a proprietary microprocessor design it had dabbled with more than 10 years ago, the MIPS license represents the first time Micron has had a processor as part of its product portfolio.

Yet Klein stressed that Micron has no intention to provide standalone processors. Rather, it will use them as a building block for integrated devices with various types of intellectual property (IP) developed internally or acquired from partners. In that sense, Micron will act as a foundry to companies it considers strategic partners, though it has no intention of playing in the same arena as Taiwan Semiconductor Manufacturing Co. (TSMC) or United Microelectronics Corp.

"We're focusing on parts that are less PC-centric," Klein said. "We intend to produce parts for people using our IP and their IP. We like to say it's a strategic foundry type of business."

Low-cost advantages

Micron expects the processor cores to serve as a vehicle to promulgate its embedded DRAM technolog y, either for outside customers or for internally developed products. Micron, one of the three largest DRAM suppliers in the world, prides itself on its low-cost manufacturing technology — among the lowest in the business, Micron claims — and now it wants to apply that expertise to a wider range of products by melding it with logic.

This is not Micron's first foray into embedded DRAM. Several years ago, it formed a partnership with LSI Logic Corp. to develop embedded DRAM, but that deal was eventually aborted in part because neither company was willing to share its process technology with the other. Later, in 1998, Micron bought graphics chip vendor Rendition with the intention of combining that company's graphics controller with on-board frame buffer memory to produce a high-performance graphics chip. Though Micron has built such a device, it has decided not to sell it as a standalone chip due to difficulty in keeping pace with the rapidly changing requirements of Microsoft's DirectX API, Kl ein said.

Despite these setbacks, Micron has never let go of the notion that embedded DRAM is a technology worth pursuing. There has been no shortage of customer requests for the technology, and many industry observers believe it is growing beyond its niche as an integrated frame buffer memory for graphics chips. And with the industry clamoring for new capacity to meet high demand, Micron is betting it will offer embedded DRAM at just the right time.

Keeping manufacturing cost to a minimum is one of the key attributes of Micron's embedded DRAM process, the company said. It is based on a 0.15-micron DRAM process technology, not a logic process that could increase logic performance but worsen DRAM cell density. The array is made up of 1-Mbyte blocks nearly identical to those used in Micron's discrete DRAMs. So alike are the structures that Micron did not even designate a separate design team for the embedded DRAM, Klein said.

The biggest difference between its pure DRAM process and the merged DRAM/ logic process is the higher number of metallization layers needed to accommodate the logic circuits. Micron uses a relatively low number of mask steps for its DRAM process, Klein said, and should find it easy to add metal layers because it already uses chemical mechanical polishing to planarize (CMP) its wafers.

"It's like a bowling alley on that top layer," Klein said. "With other processes it's like driving off a cliff. CMP lends itself really well to adding more metal layers."

Difficult downside

The downside of using a DRAM-based process is that chip makers are often prevented from enhancing the transistor speed, which degrades logic performance. For example, the high-temperature process required for forming the capacitor structure of a DRAM makes it difficult to add a layer of silicide for all the transistor electrodes, which is commonly done in logic to reduce resistance.

Klein, however, said Micron did make some changes below the metal layers to enhance transistor performa nce, though he declined to elaborate. Compared to the processes of IBM and TSMC, "we're within striking distance," he said. "For most applications we're looking at, it's a moot point. It's a low percentage difference."

Customers are most concerned about getting high DRAM density with embedded DRAM, Klein said. For this reason, Micron will use 0.15-micron design rules for the DRAM portion of a chip and 0.18-micron design rules for the logic portion. At those linewidths, a 1-Mbit block of DRAM will take up 4.06 x 1.004 mm of die area. Micron said it has fabricated a graphics device called the V4400 with 12 Mbytes of embedded DRAM, with more than 125 million transistors on the die, he said. That device will not be sold as a standalone product, however, Klein said.

Each DRAM block has a 128-bit I/O bus and tag and control logic arranged in such a way that data can flow to each 1-Mbit block independently via a crossbar switch. Klein said the company's primary goal was to keep latency to a minimum, and adj ustments were made favor a lower five-clock access latency versus seven clocks with a standard core. That lowered the bandwidth from 3.2 Gbytes/second to 2.4 Gbytes/s. But the banks run independently, so command, access, refresh and precharge times can overlap and a device can support a sustained rate of 9.6 Gbytes/s across all the banks, Klein said.

This scheme can boost the performance of a PC chip set's North Bridge by 15 percent, as Micron demonstrated on its Samurai chip set design. Micron floated the chip set several years ago, but never brought it to market because it never obtained a bus license from Intel Corp.

Micron is now in discussions with various companies interested in its embedded DRAM technology, Klein said. Possible interested parties may include designers of communications devices like Gigabit Ethernet controllers, which could take advantage of embedded DRAM for high-speed packet switching. "There's no shortage of opportunity," Klein said.