Mentor Graphics Delivers First Co-Verification Models for MIPS64 Embedded Processors
WILSONVILLE, Ore., Oct. 10 -- Extending its position as the hardware/software co-verification technology and market leader, Mentor Graphics Corporation (Nasdaq: MENT) today announced that it is the first company to deliver co-verification models of the MIPS64(TM) architecture from MIPS® Technologies (Nasdaq: MIPS, MIPSB - ). The MIPS64 5Kc(TM) will be the first of the 64-bit cores to be supported.
With the Mentor Graphics® Seamless® Co-Verification Environment(TM) (CVE) systems developers incorporating the MIPS64 5Kc core can now validate hardware/software interfaces in a virtual prototype prior to design fabrication. The process helps to ensure first-pass silicon success and helps to avoid costly and time-consuming silicon re-spins. For low-power, system-on-chip (SoC) designs in the communications, consumer and networking markets, first-pass tape-out is often the difference between product success and failure.
``We collaborated closely with Mentor Graphics in the creation of the first co-verification models for the MIPS64 architecture,'' said David Courtright, director of product strategy at MIPS Technologies. ``The Seamless Processor Support Packages for the MIPS64 product line are based on our reference Instruction Set Simulator and Bus Interface models, enabling programmers and designers to perform accurate co-verification, early in the design process, of chips and systems embedding 5Kc cores. Time-to-market is essential to the success of our customers. Embedded development tools such as Seamless reduce the development risk, providing designers with early insight into interface problems that may have been identified too late in the design process to be repaired.''
The Processor Support Package (PSP) for the MIPS64 5Kc high-performance core incorporates an Instruction Set Simulator and Bus Interface Models from MIPS Technologies. The PSP is integrated with Mentor's XRAY® high-level multi-core debugger and works with all popular logic simulation platforms, including Model Technology's ModelSim® simulation product.
``Mentor Graphics recognizes the leading role the MIPS64 architecture plays in the embedded systems marketplace,'' said Serge Leef, general manager of the SoC Verification business unit at Mentor Graphics. ``Early model support for the 5Kc core through Seamless, combined with ISS integration through XRAY, provides embedded designers with a highly-integrated support package for all stages of the early SoC design flow.''
The MIPS64 5Kc is a high-performance, synthesizable 64-bit RISC processor core optimized for low-power SoC and ASIC applications. Featuring a peak clock frequency of 310 MHz (0.13-micron process), the 5Kc core consumes just 0.5 mW/Mhz. The 5Kc core features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache.
Availability and Pricing
The Mentor Graphics Seamless CVE PSP for MIPS Technologies MIPS64 5Kc core is available now on HP and Sun workstations. Pricing is listed at $30,000 base. For more information, or to register for upcoming SoC workshops and seminars, visit the Seamless web site at www.mentor.com/seamless.
Combining the best in embedded software development tools with logic simulation, the Mentor Graphics Seamless co-verification environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.
About Mentor Graphics Corporation
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $500 million and employs approximately 2,600 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
NOTE: Mentor Graphics, Seamless, ModelSim and XRAY are registered trademarks of Mentor Graphics Corporation. Co-verification Environment is a trademark of Mentor Graphics. MIPS is a registered trademark and MIPS64 and MIPS64 5Kc are trademarks of MIPS Technologies, Inc. All other company or product names are the registered trademarks or trademarks of their respective owners.
CONTACT: Wendy Slocum of Mentor Graphics, 503-685-1145, or firstname.lastname@example.org; or Jeremiah Glodoveza of Benjamin Group/BSMG Worldwide, 415-352-2628, ext. 559, or email@example.com, for Mentor Graphics.