English
NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Panel studies power in SoCs
Ron Wilson, EE Times
(11/04/2005 6:35 PM EST)
NEWPORT BEACH, Calif. — A panel discussion at the 3rd International System-on-Chip Conference here this week attempted to skip past the academic science projects and the rosy vendor marketing and explore what was really feasible today in the challenging area of power management.
The first question the panel attacked was the need for more power management in the first place. Couldn't today's designs get by with standby, sleep, doze and coma modes, like their 180-nm predecessors?
"One sleep mode is not enough any more,” declared David Flynn, engineering fellow at ARM Ltd. "The power demands of applications now require far too many techniques."
On the issue of what to do about the problem, the panel was more divided. Steve Liebson, technology evangelist at Tensilica Inc., for his part, argued that the place to start was with architectural change.
(11/04/2005 6:35 PM EST)
NEWPORT BEACH, Calif. — A panel discussion at the 3rd International System-on-Chip Conference here this week attempted to skip past the academic science projects and the rosy vendor marketing and explore what was really feasible today in the challenging area of power management.
The first question the panel attacked was the need for more power management in the first place. Couldn't today's designs get by with standby, sleep, doze and coma modes, like their 180-nm predecessors?
"One sleep mode is not enough any more,” declared David Flynn, engineering fellow at ARM Ltd. "The power demands of applications now require far too many techniques."
On the issue of what to do about the problem, the panel was more divided. Steve Liebson, technology evangelist at Tensilica Inc., for his part, argued that the place to start was with architectural change.
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