ATE vendors cozy up to on-chip test for SoC era

ATE vendors cozy up to on-chip test for SoC era
By Jerry Ascierto, EE Times
October 6, 2000 (12:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001006S0013

ATLANTIC CITY, N.J. — With the cost of testing silicon nearly matching the cost of producing it, semiconductor companies and their test vendors are struggling to strengthen the ties that bind design tools and testers. At the International Test Conference 2000 this past week, built-in self-test (BIST) and design-for-test (DFT) dominated discussions of how to fight the astronomical costs of automated test equipment.

As embedded testers continue to gain more industry consideration, ATE companies are increasingly joining hands with BIST companies, even as the rise of BIST looks to fundamentally alter the ATE landscape.

"There's a word out in the industry right now called 'co-opetition,' " said John DiGirolamo, president and chief executive officer at BIST maker Fluence Technologies Inc. (Beaverton, Ore.). "We as an industry need to focus on the customer, even if that means cooperating with a competitor."

Indeed, the ITC was peppered with announcements of ATE and embedded-test company linkups. Some industry watchers believe the ultimate result could be a new class of streamlined ATE machines that work with BIST — and pack far less sticker shock than what's out there now.

"ATE hardware will change fundamentally in the next 18 months," said DiGirolamo. Such machines will be smaller with lowered capabilities and, therefore, much less expensive. "If you can test internally on-chip, why buy those monolithic machines?" DiGirolamo said. "The new class of machines will cost more like $500 a pin, not $5,000."

IBM Microelectronics vice president Bruce Beers urged the test industry to move toward BIST in his keynote address, which kicked off the conference. As the complexity of chip designs rises, Beers said, a compromise between ATE vendors and the BIST camp must take place.

"IBM will release between 250 and 300 ASIC designs this year," he said. "The average gate count will be 5 million, the largest being 18 million." With currently available technology, designs could go up to 40 million gates, "so the pressure is there," he said.

"If we look at the data volume required to test these products we see it's rising exponentially," Beers said. "It's getting to the point where we'll run out of space on standard buffers. We can't keep chasing this data volume paradigm forever."

Beers cited an IBM initiative, dubbed Smart BIST, which reduces I/O data volumes by as much as 10 times. "The industry desperately needs this kind of thing or we'll be test-bound as an industry," he said.

Robert Aitken, ASIC design methodology program manger for Agilent Technologies Inc., issued a similar call for unification. As design tools increasingly include aspects of test, the test industry must understand design better, he said in a speech following Beers' keynote.

The traditional lines between system design and test are beginning to blur, breeding "a new generation of design tools mergin g logic synthesis with place and route," Aitken said. "Designers need to care about test, and DFT engineers need to understand design. Synthesis tools must include DFT."

Tale of two BISTs

But does this new era of cooperation spell bad news for ATE giants like LTX, Teradyne and Credence, whose expensive testers are at the center of the issue? If it's possible to embed a tester right on a system-on-chip (SoC), why pay the exorbitant sum attached to large ATE boxes?

"The cost of test is equal to if not greater than the cost of silicon these days, and it's in the best interests of the ATE companies to address that problem," Fluence's DiGirolamo said.

Fluence is a great example of that new paradigm. A wholly owned subsidiary of ATE giant Credence Systems Corp., Fluence has inked partnerships with most of the major ATE companies — that is, most of Credence's competitors — to ensure that its BIST products can be read on any piece of ATE hardware. What's more, parent Credence r ecently took a stake in Fluence's chief competitor, LogicVision Inc. (San Jose, Calif.).

"Every year in the ATE world there's a 20 percent increase in price," said Rodger Sykes, LogicVision's vice president of marketing and business development. "The cost is getting ludicrous. Our business model dictates that we have to be able to work with all different types of hardware testers. So we've got partnerships with Credence and Teradyne and LTX to make sure their hardware is LogicVision-compliant."

At the show, LogicVision announced that another ATE vendor, Kinetix Test Systems Inc. (Milpitas, Calif.), has come into the fold. Kinetix will link LogicVision's Embedded Test products with its own semiconductor test systems.

"With the increasing design complexity of most SoC chips these days, a new set of issues emerge," Sykes said. "In multimillion-gate designs, you have to be able to reuse IP [intellectual property], so we built that into it. And we want to make our BIST as transparent as possible. On large chips, our BIST only takes up 1 or 2 percent, so there's no real estate issue."

LogicVision also released at ITC this past week a vectorless sign-off capability for its Embedded Test products. LogicVision's automation capability, used to create and integrate the embedded test controllers into the chip, also generates information about the controllers and testing to enable a vectorless "hand-off" between design and manufacturing test.

Also at ITC, Fluence announced a design win with Infineon Technologies, marrying its jitter measurement BIST product, VCOBIST, to Infineon's 0.18-micron CMOS process. Fluence also released the TDS SimValidator Direct Access Scan option, charged with increasing performance of scan-based simulation for large SoC designs.

Providing more evidence of the newfound cooperative atmosphere in test, the company also released Stil-Lynx, a database interface that complies with the IEEE 1450-1999 test interface language standard — a tool for the EDA arena.

Meanw hile, ATE heavyweight Agilent signed an agreement at the show with DFT maker SynTest Technologies Inc. (Sunnyvale, Calif.). SynTest will work with Agilent customers as they design chips with multiple functional blocks capable of being tested concurrently instead of sequentially. The result will be a lower cost of test, the companies said.

Packing functionality

"As SoC devices become more complex, manufacturers are integrating more functions on each chip," said Tom Newsom, vice president and general manger of the SoC business unit, which Agilent formally launched at the show. It will serve the SoC test market. "Testing functional blocks of SoC devices concurrently will shorten the test time dramatically."

For its part, SynTest, which plays in the EDA as well as the DFT space, said it has signed an agreement with EDA giant Cadence Design Systems Inc. (San Jose) to produce a one-pass DFT and synthesis solution for multimillion-gate SoC designs.

Customers using Cadence's Envisa logi c synthesis tool in conjunction with its synthesis, placement and routing tools will be able to utilize SynTest's technology to also perform automatic insertion of scan chains, followed by compact, high-fault-coverage automatic test-pattern generation, all in one pass.