Synopsys, Mentor spiff up design-for-test tools

Synopsys, Mentor spiff up design-for-test tools
By Richard Goering, EE Times
October 2, 2000 (3:59 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001002S0027

ATLANTIC CITY, N.J. — Synopsys Inc. and Mentor Graphics Corp. will take significant strides forward in design-for-test tools this week at the International Test Conference. Synopsys will announce the integration of its DFT Compiler and Physical Compiler products, and Mentor Graphics will roll-out a redesigned version of its boundary-scan synthesis tool. Both Synopsys and Mentor also plan to upgrade their respective automatic test-pattern generation (ATPG) offerings.

The lack of an automated test capability has been one of the most notable gaps with Synopsys' Physical Compiler, a "physical synthesis" tool that goes all the way through final placement. Users have requested that Physical Compiler provide the same test capabilities as the company's Design Compiler, which already works in concert with DFT Compiler.

Physical Compiler users will now have all those capabilities and more, because Synopsys (Mountain View, Calif.) has upgraded DFT Compiler version 2000.11 to reorder scan chains based on Physical Compiler's placement information. That's not possible with Design Compiler, which doesn't have placement information.

Added capabilities

DFT Compiler runs alongside Design Compiler — and now Physical Compiler — to provide several other capabilities. These include RTL testability analysis, automatic repair of scan design rule checking violations, and synthesis of scan chains, based on constraints for timing, area and power.

Mouli Chandramouli, product marketing manager at Synopsys' nanometer analysis and technology group, said the new integration gives Physical Compiler users a "one pass" test capability. Until now, he said, Physical Compiler users have had to use a third-party placement and routing tool for scan-chain ordering.

Further, said Chandramouli, the integration decreases wiring congestion. "We've run a lot of benchmarks and we see easily 10 to 15 percent less wir ing congestion," he said. "It also optimizes the scan-chain ordering. Another big advantage is timing closure — setup and hold time violations on the scan chains are all fixed."

To the user, DFT Compiler appears as a command that can be issued from Physical Compiler. The scan synthesis and scan-chain ordering run as automatic processes without user intervention.

DFT Compiler 2000.11 will ship in December. The starting price is $15,000.

Revamped tool

Mentor Graphics (Wilsonville, Ore.) is also revamping an existing test synthesis tool, BSDArchitect, which generates synthesizable RTL descriptions of boundary-scan circuitry along with a verification testbench.

Until now, BSDArchitect has been a third-party tool resold through an OEM agreement with Alternative System Concepts (Windham, N.H.). The BSDArchitect New Edition, which replaces the existing offering, represents Mentor's own technology. New Edition is a "rewrite from top to botto m," said Ian Burgess, product marketing manager for Mentor's design-for-test division.

"The rationale of what we've done is to gain more control over our own destiny and add further enhancements to the functionality," said Burgess.

New features include automatic synthesis of I/O pads, which can save two weeks compared to manual implementation, according to Burgess. BSDArchitect New Edition also adds the generation of dc parametric tests. Finally, it provides direct control of memory built-in self-test (BIST) architectures by synthesizing interfaces to memory structures.

BSDArchitect New Edition has a new synthesis kernel, parsers and netlisters, yet claims an identical look and feel to the previous BSDArchitect. The New Edition version is available now priced at $50,000.

In the ATPG area, Synopsys and Mentor compete head-on. Synopsys' offering is TetraMax ATPG, which this week adds a sequential test-generation capability.

TetraMax ATPG until now offered combinatorial and "limited sequent ial" test generation, said Robert Ruiz, product marketing manager from Synopsys' nanometer analysis and test group. "The tool works well on many designs that adhere to clean DFT rules, but when not all rules can be adhered to, the user needs extra ATPG power to get more coverage," he said.

With sequential test-pattern generation, TetraMax ATPG improves coverage for embedded memories, large register arrays, and legacy blocks with limited scan. Many designs have shown a 5 to 10 percent improvement in test coverage, Ruiz said. And that's important, he noted, citing figures showing that increasing coverage from 93 to 97 percent can result in a 50 percent decrease in defective parts shipped.

TetraMax ATPG 2000.11, with the sequential capability, ships in December starting at $33,500.

Mentor's FastScan already handles both combinatorial and sequential ATPG, said Greg Aldrich, product marketing manager for Mentor's design-for-test division. What's new with this week's FastScan 2001 release is pattern-co mpression capabilities aimed at designs with multiple clocks.

Pattern compression is becoming an important issue for deep-submicron ICs. Fred Cohen, general manager of Mentor's design-for-test division, noted that test vector data typically takes around 500 bytes per gate — leading to test vector sets in the gigabyte range for multi-million gate ICs.

FastScan 2001, said Aldrich, has new algorithms that can reduce test patterns by 20 to 60 percent while maintaining the same level of coverage. Another new feature is synchronous macro test, which lets users test small, embedded memory blocks that aren't big enough to justify BIST techniques.

FastScan 2001 also adds a fault-sampling capability and a Unix K-shell command line environment. The upgraded product is available now starting at $92,400.