PHOENIX EDA vendors came to the High-Density Interconnect (HDI) Expo with package design tools capable of handling more complex IC packages as well as the multichip, system-in-package solutions that are becoming the poor man's answer to the system-on-chip.
Always an important link in the technology food chain, packaging has seen its value-add soar. Dataquest Inc. predicts that IC packaging revenues will double, to $50 billion, over the next three and a half years. Chip-scale packages alone will experience 100 percent annual growth in the 2000-2003 period, as "the DIP [dual in-line package] goes away," said Dataquest analyst Jim Walker.
With change sweeping the back end of the semiconductor industry, and with relatively flat growth in the market for pc-board design tools, EDA took up the packaging opportunity. As EDA vendors promised seamless and complete physical design environments, users voiced the usual complaint: that non-cooperation among the major EDA vendors had stymied standards for data exchange among tools. But participants at the Phoenix HDI Expo noted that no industry-sanctioned standards body has taken on the issue of data-exchange formats.
"The physical design tool market has been so segmented, but there is a convergence of technologies as signal integrity issues, for example, force companies to ask more of their design tool vendors," said Paul Ewing, vice president of Zuken USA Inc. Zuken Japan's only major EDA vendor, based in Yokohama plans to leverage its position in board design to gain share in package design.
Zuken announced a 3-D module for its Advanced IC Packaging Solution product. Working with Amkor Technology Inc. (Chandler, Ariz.), Zuken will support designs of stacked-dice packages, providing 3-D views of multiple dice without the need for physical models. (On the board front, Zuken also announced that it plans to convert its Hot-Stage prototyping software to a constraint-driven design flow by 2002.)
Zuken, like Cadence Design Systems and others, provides links to Ansoft's 3-D tools, which are widely used in the industry. "Our customer base wants to bolt on more Ansoft tools, and we support that," said Ewing.
Cadence came to HDI Expo to unveil Spider Route, an automatic router that will be bundled into a forthcoming version of the company's Advanced Package Designer (APD).
Joel McGrath, a former Digital Equipment packaging engineer who is the technical marketing manager for the APD product, said that instead of adapting a pc-board router to the packaging domain, Cadence developed Spider Route specifically for automatic, all-angle package routing. The router is constraint-driven and delivers "correct by design" routes if the physical and electrical constraints are defined properly, McGrath said.
"Routing has become the bottleneck in package design. That is what is taking up all the time," he said.
The router will be bu ndled with a version of APD that goes to beta customers this month, with a full release planned by the first quarter. Cadence is refining the signal integrity analysis functions and is supporting system-in-package simulation and design.
Some competitors argue that Cadence is playing catch-up. Such companies as Zuken, PADS Software (now part of Innoveda Inc.) and Avanti introduced automated package routers over the past few years in the wake of Cadence's acquisition of Cooper & Chyan Technology, which had supplied routing technology to much of the packaging industry.
Innoveda (Marlboro, Mass.) last week announced the completion of its merger with PADS Software, which has about 60,000 seats worldwide for its PowerBGA package design tool. Kevin Rinebold, product marketing manager for the PowerBGA product, described a modified strategy for PowerBGA: Rather than spend its resources going head-to-head with Cadence, Avanti and Mentor at the large contract packaging companies, Innoveda will concentrate its r esources on meeting the needs of packaging engineers working for IC vendors.
The packaging contractors in Asia are "all at capacity in terms of design. They just can't find enough skilled people, so they are pushing back on the IC companies to do more of the package design," he said.
The chip vendors in turn are working to nurture in-house package design teams and get their chip designers more involved in the initial phases of package design.
"There has to be some visibility into the package by the chip designer. To make our tools more receptive for the chip designer, we are adding functions to PowerBGA to automate and add functions to the tool," Rinebold said.
In many cases, designers will export data from PowerBGA to the more expensive tools marketed by Cadence, Avanti, Mentor and Zuken, Rinebold said. But he declined to say what data exchange formats would be supported in the updated version of PowerBGA, expected to debut in November.
With PADS now part of Innoveda, the package design tool will be linked more closely to Innoveda's signal integrity analysis and pc-board design products.
"We want to focus on the semiconductor and systems companies, on the package design engineers there," said Rinebold. "And the IC designers need to be involved in order to come up with feasible packaging designs.
"If a company sends a chip design out to a contract package company and then finds out that its packaging plan is not feasible, that can cost the IC company two, three or four weeks, which is disastrous in many markets."