AUSTIN, Texas LSI Logic Corp. and Lexra Inc. have separately introduced synthesized processor cores with enhanced DSP functions. LSI Logic is touting the best-in-class performance of its core, while Lexra is promoting its core's reduced power consumption.
LSI Logic (Milpitas, Calif.) said its the ARM966E-S, a synthesized version of the ARM9E core, will be offered to customers as part of its CoreWare library. Rafi Kedem, director of ARM CoreWare product marketing at LSI Logic, said other ARM licensees will find it hard to beat the core's performance. "There were doubts within the ARM camp that the ARM9E architecture could be taken to 200 MHz, but we have done that," Kedem said.
Meanwhile, Lexra (Waltham, Mass.) has squeezed power out of the LX5180 RISC-DSP core, which is aimed squarely as an ARM9E competitor. Charlie Cheng, chief executive officer of Lexra, said the LX5180 is a fully synthesizable core that delivers much higher DSP perform ance than the ARM9E, at roughly the same power consumption. Lexra used extensive clock-gating techniques in the design to hit the power consumption needs of customers in the consumer electronics industry, Cheng said.
LSI Logic's Kedem drew a distinction between a synthesizable core and one that has been synthesized in an optimal way to a specific library. LSI Logic is in the latter, synthesized camp, he said.
The ARM9E the E indicates DSP extensions architecture was developed as a synthesizable architecture, but not as a custom design, by ARM Ltd. "The traditional hard-core approach doesn't have the flexibility that the designers need," Kedem said. "For SoC [system-on-chip] designs, trying to achieve timing closure is very difficult in a traditional ASIC approach. And with a synthesized core, there is the ability to easily move the design to a more advanced process." LSI Logic engineers created a pre-laid-out, synthesized core that had been optimized for the company's 0.18-micron proce ss. At the Microprocessor Forum in mid October, LSI Logic engineers will describe a synthesized MIPS core that runs at 250 MHz, Kedem said.
The ARM966E-S is a non-cached core that draws about 1 milliwatt per megahertz of operation. It delivers about 1.15 Mips per MHz; the static design can be clocked anywhere between zero and 200 MHz. Based on a five-stage pipeline that can perform a 16 x 32 multiply accumulate operation in a single cycle, Kedem described the 9E as a core with "moderate" DSP capabilities. For heavy-duty DSP functions, LSI Logic steers customers toward the company's ZSP DSP cores, which can be bolted alongside the 966E-S via ARM's Amba bus.
Because it supports the Amba 2.0 high-speed bus standard, the 966E-S core can serve as a "master processor" in a device. "One reason why ARM has been so successful in the marketplace is that they have solved the tool issue for the bus, which is a free-license bus that is supported by about 40 licensees," Kedem said.
The Harvard architecture imp lementation features zero wait states for tightly coupled instruction and data cache, which are necessary to support deterministic performance in embedded applications. Code can boot from a flash memory into tightly coupled SRAM. In addition, the core includes a real-time trace macrocell for in-circuit emulation on a PC host.
Kedem said another advantage is that the DSP extensions to the ARM9E instruction were defined by ARM, and are standard across the various vendors.
Lexra developed its Radiax extensions to the MIPS Industry Standard Architecture (ISA) to bring DSP functionality to the MIPS architecture, Cheng said. The extensions appeared first in the LX5280 "RISC plus DSP" core introduced last year. While the superscalar LX5280 can run as fast as 200 MHz, prospective customers in the consumer space told Lexra that the core's power consumption was too high.
"Companies rarely go back to a design, but we went to the 5280 and scrubbed the entire thing," Cheng said. "F or the LX5180 we created a uniscalar core with extensive clock gating to reduce power consumption. The data cache can be turned off at any time itself a major power savings."
While the processor core typically consumes less than 10 percent of a chip's area, power consumption is another matter: Lexra estimates that the processor core consumes about 40 percent of total power in a design produced with a 0.18-micron or 0.13-micron process. The LX5180 draws 0.8 mW per MHz, compared with 0.65 mW per MHz for many existing ARM9E implementations, Cheng said.
For certain commonly implemented algorithms, the LX5180 requires far fewer processor cycles than other implementations, Cheng said. By comparing published data from ARM vendors with its own benchmarks, Lexra claims that the LX5180 can do a vector dot product (in which two matrices multiply themselves) in far fewer cycles. For a complex fast Fourier transform, the LX5180 requires roughly half as many processor cycles as an ARM9E, Cheng said.
Le xra is targeting the LX5180 at such systems such as portable DVD players, portable videogame machines, voice-over-Internet Protocol gateways and networking systems, Cheng said. A digital camera IC based on the LX5180 will go into production in the first quarter of next year, and five other designs are expected from Lexra customers in the second half, Cheng said. "Our strategy is to offer roughly the same amount of power consumption as an ARM9E, but to do three times as much work for certain applications," he said.
As a company, Lexra is moving toward products that "innovate on the MIPS ISA to provide more margins and higher ASPs [average selling prices], with cores that enable a whole new class of products in the communications market," he said.
Lexra, which has fewer than 40 employees, expects revenues this year to be slightly less than $10 million, or double its 1999 revenue, Cheng said.
A per-project license for the LX5180 costs $425,000, with per-chip royalties of $1 in quantities up to 500, 000, and less for higher-volume production runs.