Intel's XScale architecture debuts in network-processor chip set

Intel's XScale architecture debuts in network-processor chip set
By Mark LaPedus, Semiconductor Business News
September 27, 2000 (4:21 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000927S0078

SAN JOSE -- At the Embedded Systems Conference, Intel Corp. today announced the first in a family of chips based on its new RISC-based processor architecture for networking, storage, and related markets.

The Santa Clara, Calif.-based chip giant is offering a two-chip solution designed for use in I/O processing applications, such as computer storage peripherals, storage-area networks (SAN), media-streaming, and other systems. The two-chip solution includes the new Intel 80200 network processor and IOP312 I/O companion IC. The chip set itself is called the IOP310.

A key to the chip set is the 80200, which is the first product based on Intel's recently introduced XScale architecture (see Aug. 23 story). XScale is based on the Intel's StrongARM RISC core and designed to enables the processor to support a wide range of different frequencies and power-management standards.

The 80200, combined with the IOP312, is an ideal solution in high-performance I/O applications, said Tom Franz, vice president and general manager of Intel's Network Processing Group. "People are putting more and more demands on the infrastructure," said Franz, during a press event at the Embedded Systems Conference today. "Storage is in integral part of the network-attached [infrastructure.]"

In an interview after the event, Franz said Intel is targeting its IXP1200 network-processor lines for packet-processing applications. The IOP310 chip set is geared for I/O applications, he added.

Based on a 32-bit RSIC architecture, the 80200 chip itself is offered at several clock speeds, including 333-, 466-, 600-, and 733-MHz. At 733-MHz, the IC has a power dissipation of less than 1.3-Watts.

The 80200, which consists of a 7-stage, 8-stage superpipelined core, also includes a 66-MHz PCI bus, 32-Kbytes of data cache, and 2-Kbytes of mini-data cache.

The IOP312 chip itself is said to be 300% faster than the com pany's previous I/O processors based on the i960 architecture. Included on the IOP312 is a 100-MHz internal bus, which provides a total bandwidth of 800-Mbytes. It also includes a 64-bit, 66-MHz PCI-to-PCI bridge.

The IOP310 I/O Processor chip set is $70 for the 333-MHz version and $93 for the 600-MHz version. These products are sampling, with production slated in the first quarter of 2001. The 733-MHz version will be sampling shortly after these products, Intel said.