APTIX ANNOUNCES SHIPMENT OF EXPEDITION: SYSTEM-ON-CHIP DESIGN MAPPING TOOL FOR RAPID SYSTEM EMULATION
New Interactive Software Simplifies the Emulation Process, Increases Predictability of Results
SAN JOSE, Calif. - September 26, 2000 -- Aptix Corporation today announced shipment of an interactive emulation software environment enabling fast, efficient and predictable creation of prototypes for system-on-chip (SOC) devices directly from RTL designs. Unlike any tool available today, the environment is unique in its ability to run directly from register transfer-level (RTL) design information and ensure 100% Synopsys-compliant RTL compilation.
The environment, Expedition(tm) emulation software, automates the RTL design mapping process allowing users to focus on verifying and debugging SOC designs. The tool automates the set-up of complex electronic circuits for Aptix's popular System Explorer prototyping tools. As a user-friendly environment, the software organizes and controls the flow of data between the various emulation preparation steps, making emulation easier and shortening the time-to-in-circuit operation.
The software is built around proven technology deployed by Aptix's prototyping services arm for its customers. The package is a front-end tool for Aptix's popular System Explorer(tm) reconfigurable prototyping tools, which map RTL design descriptions to FPGA logic netlists by incorporating logic synthesis and hierarchical partitioning functions within an intuitive, wizard-like graphical user environment.
"In addition to significantly reducing time-to-emulation, Aptix's Expedition software and the simple-to-use graphical user interface built on the latest Java technology, help customers to get new design teams up to speed quickly, resulting in significant productivity gains," said Raj Mathur, Product Manager of Expedition.
The Expedition package encapsulates Synopsys' FPGA Compiler II software and a hierarchical Partitioner. Expedition software increases the productivity of engineers employing Aptix's unique block-based prototyping methodology where each RTL block within a complex design is mapped and verified against its test bench as an independent circuit. "This approach reduces the time to achieve full design in-circuit emulation, because the design mapping is done in parallel with the hardware RTL design creation and simulation process, " said Raj Mathur.
The resulting reconfigurable prototype of the design is used to integrate all design blocks and accelerate software integration and debugging. By identifying design problems early in the design cycle, customers have the flexibility to address problems in the most effective manner. This is a welcome proposition to engineers who previously have been forced to implement sub-optimal fixes in the form of software workarounds late in the development process.
Expedition is a complete software environment. The primary elements are as follows:
- Verilog and VHDL parsers and syntax checkers.
- Synopsys' FPGA Compiler II software ensures users that circuits they prototype and verify in the System Explorer environment will be equivalent to ASIC designs created by Synopsys' Design Compiler tool. Expedition optionally provides users the flexibility of top-down or bottom-up synthesis offering maximum flexibility of trade-offs between design complexity and synthesis run-times.
- Hierarchical partitioning software that analyzes the user's netlist top-down to automatically group blocks within the hierarchy, achieving fast, flexible implementation in multiple FPGAs. Feedback in graphical form of the FPGA resource utilization provides guidance for users to interactively optimize the FPGA mapping for speed and density.
- Automated set-up of the Module Verification Platform(tm) (MVP(tm)) co-emulation interface for linking the prototype hardware to the customers' simulation software environment
- Memory compiler for automated development of user-defined memory
About Aptix Corporation
Aptix products are used to verify system and system-on-chip (SOC) device Aptix Corporations' products are used to verify system and system-on-chip (SOC) designs prior to integrated circuit (IC) and board tape-out and fabrication. Aptix' products utilize the block-based verification methodology, which provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. This methodology shortens the net prototype creation time to achieve real-world operation of the prototype to the few days required to map and verify the last RTL block designed. Debugging designs becomes simple because the mapping process is both under the users interactive control and follows the natural hierarchy of the design. This also makes tracing design problems back to the source netlist an intuitive process.
The company is privately held and is headquartered at 2880 North First Street, San Jose, Calif. 95134.
Telephone: (408) 428-6200
Fax: (408) 944-0646
Visit Aptix on the Web at: http://www.aptix.com
FOR MORE INFORMATION, CONTACT:
|LINDA LAVIN |
Telephone: (408) 428-6297
Fax: (408) 944-0646
|LEANNE FRANK |
Public Relations Counsel
Telephone: (503) 221-7403