Lithographic Shrink Provides Easy Path to Increased Profit for Customers
Hsinchu, Taiwan, R.O.C. – January 18, 2006 -- Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM) has entered full production of its 80 nanometer (nm) “half-node” process technology for high-performance designs.
With this process, designers can improve performance and reduce the overall size of their designs by up to 19 percent, resulting in more die per wafer and more than 20 percent cost-per-die reduction.
"TSMC offers the half-node as an extra option to our customers," said Jason Chen, Vice President of Corporate Development for TSMC. "The potential performance, die area and yield improvements, coupled with the cost-per-die savings, provide a clear competitive advantage and easy shrink path for our customers."
"Using the latest processes brings cost and performance advantages to our graphics chips," said Rich Heye, Vice President and General Manager of Desktop, at ATI. "Being first to 90nm gave us the lead in performance and features and moving to 80nm will improve our costs, too."
"NVIDIA and TSMC have a longstanding strategic collaboration involving half-node technologies," said Chris Malachowsky, Senior Vice President of Engineering and Operations, NVIDIA. "The ability to quickly port a design to a new technology with higher performance and a smaller footprint is a powerful tool in a competitive, consumer oriented market."
The 80nm process is a lithographic shrink of the 90nm process technology. As a consequence, this node supports most of 90nm TSMC and third-party libraries and IP requiring only simple re-characterization using 80nm models. Design rules are also a linear shrink from 90nm. The result is a significantly reduced re-design time to port the chip to the new process.
TSMC has a history of success with its unique half-node strategy. The company first began offering half-node processes at the 0.35-micron generation (with the half-step 0.30-micron), followed by the 0.25-micron (half-node 0.22), 0.18-micron (half-node 0.16), and 0.13-micron (half-node 0.11) generations.
In each case, high-volume leaders in various markets have seen significant strategic and financial advantage by employing half-node processes.
The first 80nm process in production is TSMC’s high-performance GT process, which will be followed next month by the high-speed HS process and low power LP processes in March 2006. A special GC process, which provides both low active and standby power advantage, will become available in the third quarter of 2006.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to run 65nm customer design prototype wafers. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.