Toshiba Adds Multi-Protocol High-Speed SERDES I/O Core Family That Meets High Speed Requirements of Storage, Networking, Consumer and Gaming Markets

Designed in the Toshiba 90nm Process for Small Silicon Footprint and Reduced Cost; Scalable for More than 64 Ports of Fibre Channel

SAN JOSE, Calif. January 24, 2006 — Toshiba America Electronic Components, Inc. (TAEC)* today announced a new multi-protocol, high-speed SERDES I/O core family of products for 1/2/4 gigabit per second (Gbps) Fibre Channel, 10-gigabit Ethernet, 1.5/3.0Gbps Serial ATA (SATA) and 1.5/3.0Gbps Serial Attached SCSI (SAS) applications. The Fibre Channel PHY cells support implementations of protocol controller, switch and disk drive ICs for such applications as host bus adapters, fabric, director edge and core switches and storage arrays. The core has one of the smallest silicon footprints in the 90 nanometer (nm) process node and is scalable for more than 64 ports of Fibre Channel. This core includes a new rate selectivity feature that allows auto negotiation with uncompromised jitter performance in the system. Other key features include receiver (Rx)/transmitter (Tx) equalization, clock multiplexing and SATA spread spectrum clocking. The cores are currently available for customer design-in.

"Toshiba is committed to providing the silicon-proven, high-speed interfaces required for the custom SoC market and our new multi-protocol, high-speed SERDES I/O core family of products is another step forward," said Dr. Rakesh Sethi, director of business development in the Custom SoC and Foundry Business Unit at TAEC. "We've deployed a single core to address the Fibre Channel, SATA, SAS and chip-to-chip connectivity platforms. Our solution allows integration of multiple cores as high as 128 Rx/Tx on a single chip and uses Toshiba 90nm process technology for low power, reduced cost and one of the smallest 90nm footprints in the industry. We have validated the core on silicon and customer applications ranging from 1/2/4Gbps and SATA Gen1 and Gen2."

The family of products makes optimum form factors achievable, while minimizing power consumption and enabling high-port densities. The cells allow rate selectivity on a per channel basis for mixed systems using 1/2/4Gbps Fibre Channel and 1.5/3.0Gbps SATA/SAS. Dr. Sethi explained that "this rate selectivity feature with intelligent switching results in fewer clock resources on the board and a lower bill of material cost for our customers." The core maintains compatibility to legacy systems as both Rx and Tx can operate at different data rates and can support auto negotiation controlled by a high level. In addition, the core can handle legacy voltage levels up to 2 volts (V) peak-to-peak differential output on the Rx and Tx cells. Both 50 and 75 ohms termination is supported. Tight jitter performance allows for ease of support in SAS and SATA applications.

Main Features

• Designed in the Toshiba 90 nm process for small footprint and reduced cost
• Scalable for more than 64-ports of Fibre Channel
• Each Rx and Tx is independently programmable to run at 1.0625, 1.5, 2.125, 3.0, 3.1875 or 4.25Gpbs to allow independent auto negotiation
• Tx are hot pluggable for improved reliability
• Features on-chip programmable 100/150 differential termination, enabling compatibility with legacy systems
• Has low system-power consumption with global as well as per-receiver and per-transmitter power-down modes
• Has advanced pre-emphasis and Rx equalization to support high-loss legacy channels and allow interoperability with other system components with no additional support
• Can set serial data rates and parallel interface data path widths independently for improved flexibility
• Provides great degree of design freedom with user-configurable input/output data polarity
• Transmitter features differential CML outputs with no rise time control, fully programmable 4-tap transmitter pre-emphasis, adjustable output drive levels to minimize power and crosstalk and configurable Tx CDR to allow tracking of plesiochronous data sources
• Receiver features differential CML signaling that operates with direct and AC-coupled inputs. On-chip configurable receive equalization (6-bit) provides 0 - 6dB gain and the configurable Rx CDR supports SATA spread spectrum clocking (SSC). It detects loss of reference clock and loss of lock with a lock time in 512-bit times.
• Reference Clock supports 106.25 to 622 megahertz input clock rate with two individually selectable reference clock inputs for each serial link
• Offers Fibre Channel and other standards support including support for 1.0625Gbps, 2.125Gbps and 4.25Gbps Fibre Channel - Physical Interface (FC-PI) links, 3.1875 10-Gigabit Ethernet, 1.5 and 3.0Gbps SATA, and 1.5 and 3.0Gbps SAS
• Has 1.8V driver and 1.2V core-logic power supplies
• Has support for Flip Chip BGA and wire bond packages

About the 90nm TC300 Family of Custom SoCs
The TC300 family of custom SoCs is designed for applications needing high performance with a small die size. The 90nm custom SoC family employs high-density gates, memories, I/Os and interconnect structures and is well-suited for systems above 300MHz or 5 million gates. Three library options for low power, high speed and very high speed may be mixed and matched in designs to permit optimum performance with a small die size and low power. Toshiba has delivered more than two-dozen 90nm designs in volume production over the last year and over 15 million chips in 90nm since 2004.

Availability
The core is currently available for customer design-in. Volume production is planned to start in the second quarter of 2006. For a product brief, please visit:
http://www.toshiba.com/taec/adinfo/socworld/literature.html.

*About TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes memory and flash memory-based storage solutions, a broad range of discrete devices, displays, medical tubes, ASICs, custom SOCs, microprocessors, microcontrollers and wireless components for the computing, wireless, networking, automotive and digital consumer markets.

TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba Corp. (Toshiba), Japan's second largest semiconductor manufacturer and the world's ninth largest integrated manufacturer of electric and electronic equipment. In almost 130 years
of operation, Toshiba has recorded numerous firsts and made many valuable contributions to technology and society. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.