VeriSilicon Tapes out Flip-Chip Design With Cadence Encounter

January 24, 2006 -- VeriSilicon Holdings Co., Ltd. (VeriSilicon), a leading ASIC design foundry, today announced that VeriSilicon has successfully taped out a complex, high-speed, flip-chip SoC using an automatic flip-chip flow based on the Cadence® Encounter® digital IC design platform.  VeriSilicon achieved first silicon success on the SoC, which is in volume production.

With SoC Encounter, VeriSilicon reduced the chip’s die size, increased performance, improved timing optimization, and achieved better power integration. These benefits provided important advantages on the flip-chip design, which has a die size of 8.4x8.4mm2, 1.6 million gates, and 6 main clocks running at 250MHz.  The design’s packaging is a BGA729 Flip Chip, based on the SMIC 0.15um LV 1P7M process.

“As an ASIC design foundry, VeriSilicon is consistently looking for ways to improve the design flow to better serve customers. The greatest challenge in implementing a flip-chip SoC lies in the automatic flip-chip flow, such as automatic bump assignment and RDL routing,” said Nianfeng Li, vice president of design methodologies at VeriSilicon.  “The Cadence SoC Encounter system works smoothly on top of the VeriSilicon Standard Design Platform (SDP) and our special I/Os, and its advanced features helped us greatly speed up the flip chip design process.”

The Cadence SoC Encounter system helped VeriSilicon in IO pad optimization based on bump location and assignment, bump re-assignment based on pad location, automatic RDL routing with user-specified constraints, and multiple routing widths.  It also automatically connected power cells to bumps, and used verification support with verify commands and automatic bump placement. Encounter QRC was used for manufacturing-aware parasitic extraction, while VoltageStorm® was used for power analysis.

“We are very happy that VeriSilicon chose the Cadence Encounter design flow to develop this flip-chip SoC,” said Wei-Jin Dai, corporate vice president at Cadence. “Automatic bump assignment and RDL routing reduced the overall schedule time, while delivering a significantly improved Quality of Silicon (QoS) for this design. Encounter’s integrated design flow was an important factor in reducing time-to-market.”

About VeriSilicon

VeriSilicon Holdings Co., Ltd. is a fabless ASIC design foundry focusing on providing semiconductor IP, design services and turnkey services including manufacturing, packaging, testing, and delivery. VeriSilicon has operation centers in Shanghai, China, Silicon Valley, US, Taipei, Taiwan, and Tokyo, Japan to service worldwide customers. Over 500 customers worldwide have licensed VeriSilicon’s IPs and Standard Design Platforms (SDPs), including standard cell libraries, IO cell libraries, memory compilers, optimized specifically for wafer foundries such as, Semiconductor Manufacturing International (Shanghai) Corporation (SMIC), Grace Semiconductor Manufacturing Corporation (GSMC), Advanced Semiconductor Manufacturing Corporation of Shanghai (ASMC) and Shanghai Hua Hong NEC Electronics Co., Ltd (HHNEC), and HeJian Technology (Suzhou) Co., Ltd. (HJTC), covering 90nm, 0.13ìm, 0.15ìm, 0.18ìm, 0.25ìm, 0.35ìm, and 0.6ìm process technologies. VeriSilicon has achieved the first silicon success and started volume production of many complex, multi-million gates ASICs using 0.18 um and below technologies at China based wafer foundries. VeriSilicon is the first and only ARM certified design center (ATAP) and the first and only LSI certified ZSP design center in mainland China. In 2005, VeriSilicon was ranked number three in Deloitte Technology Fast 50 China, the top 50 fastest-growing technology companies in China and number six in Deloitte Fast 500 Asia Pacific, the top 500 fastest-growing technology companies in Asia Pacific. VeriSilicon was also named one of the Red Herring 100 Private Companies of Asia, and selected as one of the EE Time 60 Emerging Startups. For more information, please visit http://www.verisilicon.com.