Denali Deploys IP for PCI Express 2.0 Products to More Than 80 Customers
PALO ALTO, Calif., January 25, 2006 -- Denali Software, the world leader in Electronic Design Automation (EDA) and Intellectual Property (IP) products for standard semiconductor chip interfaces, today announced that its PureSpec™ product is the first verification IP to support the evolving 2.0 version (Gen II) of the PCI Express™ specification.
More than 80 customers currently using Denali's PureSpec verification IP for PCI Express version 1.1 now have access to PureSpec for the latest (0.7) version of the Gen II specification. PureSpec also supports the most recent update to the PIPE specification for Gen II, which enables the development of functionally equivalent PHY interfaces.
Denali's PureSpec™ verification IP software for PCI Express is the most widely used solution for verifying functionality, compliance and interoperability of PCI Express designs at the pre-silicon stage of chip or IP core development. Previously announced customers using PureSpec for PCI Express development include: Agere Systems (NYSE: AGR), Atheros Communications (NASDAQ: ATHR), NVIDIA Corporation (NASDAQ: NVDA), Rambus (Nasdaq: RMBS), Sun Microsystems (NASDAQ: SUNW), and Unisys (NYSE: UIS).
"Our PureSpec product that supports PCI Express Gen II has been deployed with key customers for several months now," says David Lin, vice president of product marketing for Denali. "As the leader in verification solutions for PCI Express technology, our customers rely upon Denali to deliver early access to high-quality verification solutions for PCI Express designs. Our PureSpec product is in sync with the latest revisions from the PCI-SIG, and we continue to track the specification and provide our customers with updates as they occur."
PureSpec supports both PCI Express version 1.1 and Gen II revision 0.7. It includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the root complex, switch, endpoint and PCIe to PCI bridge. Generic devices conforming to the specification can also be emulated. Composite configurations by port, function or virtual channel are also supported. In addition to the comprehensive coverage of the PCI Express version 1.1 specification, PureSpec feature enhancements for PCI Express Gen II include Access Control Service (ACS), Function Level Reset (FLR), speed negotiation and the new PIPE specification.
Denali is an active member of the PCI Special Interest Group (PCI-SIG) electrical working group (EWG) which is specifically chartered with defining the PCI Express Gen II specification. While maintaining backward compatibility with the 1.1 version of the specification, the Gen II specification provides numerous improvements designed to address increased bandwidth and networking and embedded and computer applications.
About Denali
Denali Software Inc. is the world's leading provider of Electronic Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's Databahn™ and Dataplex™ IP products provide control and optimal data throughput for external DRAM and Flash memory devices. The PureSpec™ and MMAV™ verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, ASI, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's Blueprint product provides complete solution for on-chip register design and management. For more information, visit Denali at http://www.denali.com, call (650) 461-7200 or email info@denali.com.
|
Related News
- NetEffect Adopts Denali's PCI Express 2.0 and IO Virtualization Technology Solutions
- ConnectX InfiniBand Adapters and 10Gb Ethernet NICs Designed for PCI Express 2.0 Technology with Denali PureSpec Verification IP
- LSI Adopts Denali's PCI Express 2.0 Solutions to Streamline RAID Technology
- Denali Announces PureSuite Product for PCI Express 2.0 Technology
- Synopsys Releases Silicon Proven 5.0 Gbps PCI Express 2.0 PHY IP
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |