Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
Gliwice & Bielsko-Biala, Poland -- January 25, 2006
- The silicon Intellectual Property (IP) provider, Evatronix S.A., announced today successful accomplishment of the certification procedure for compliance of its USBHS-OTG-SD-S controller core to the Universal Serial Bus 2.0 specification and its On-the-Go supplement. The compliance testing procedure took place at the 50th USB Implementers Forum Compliance Workshop between 14th and 18th of November in Milpitas, California.
After certification procedure results have been approved by USB Implementers Forum.
Evatronix core has been listed on the USB-IF Integrators List and has gained the right to bear the USB On-The-Go Hi Speed logo.
The reference design submitted for compliance testing of the USBHS-OTG-SD-S core was a mass storage class design, implementing host and device operation modes and consisting with a handful of Evatronix IP cores (including R80515 8-bit microcontroller core as well as ATA Interface controller) all implemented in the Xilinx FPGA and assembled with other components on the prototyping board. PHY chip with ULPI (UTMI+ Low Pin Interface) from independent partner was used in this design.
”We are very pleased that we tested our solution for compliance to USB OTG HS specification according to USB-IF certification procedure” says Wojciech Sakowski, Evatronix President & Chief Strategy Officer. “Last year when the earlier version of the core was launched to the market the compliance testing procedures for the OTG equipment running in High Speed mode were not formally approved and we could only got it certified for USB OTG Full Speed mode compliance, although it supported High Speed mode already at that time. USBHS-OTG-SD-S and other Evatronix USB controller cores
Featuring high-compatibility and easy–integration USBHS-OTG-SD-S offers very efficient solution for designers. It could be used as dual role device operating as USB host ( Low-, Full- and High-speed modes) or USB peripheral ( Low-, Full- and High-speed modes) device. The full OTG Dual role device solution allows designers to achieve device-to-device connectivity between any of mass storage applications, audio/video applications, communication devices, digital cameras, networking, Digital Media Controllers.
Adjusting the USBHS-OTG-SD-S core to the requirements of target applications is straightforward thanks to its configurability that includes configuration of the size and direction of endpoints, type of host processor interface as well as physical interface. The latter one is a UTMI+ compliant (either 8 or 16-bit) but the controller may be connected to ULPI PHY interface through a dedicated wrapper. Using ULPI is especially useful for applications where PHY layer is implemented as a separate chip instead of being integrated into system-on-chip that contains the controller. Reduced number of external pins (just 13 pins are needed to interface controller to the transceiver) is of utmost importance then.
Along with USBHS-OTG-SD-S Evatronix offer also includes USBHS-OTG-MPD core – the most efficient OTG controller because of internal USB-aware DMA master module, with improved architecture and changed the packets buffering algorithm, demanding less on-chip memory in compare to the other USB designs. Hardware implemented split transactions allow full support for the hubs. Two external AMBA AHB interfaces: one for DMA and one for the register set, allow the designers to make very efficient USB system.
In the USB design group there are also: peripheral 1.1 and 2.0 controller cores with many types of external interfaces. Because of configurability of UTMI interfaces, any core can be derived with UTMI or ULPI interface – UTMI/ULPI wrapper is then added. Availability and deliverables
USBHS-OTG-SD-S core is available today from CAST, Inc. or its sales partners and in continental EU countries also directly from Evatronix.
As all Evatronix IP cores USBHS-OTG-SD-S is delivered in a VSIA standard compliant package containing either RTL source code (VHDL or Verilog) or a netlist targeted towards chosen FPGA technology, self-checking testbench, test suites, simulation and synthesis scripts as well as set of comprehensive documentation covering detailed functional specification, integration manual and verification spec. Furthermore, in order to facilitate USB technology exploration, Evatronix provides a USB software stack. The software is available in two versions: one optimized for 8-bit microcontrollers and one suitable for 32-bit processor based embedded systems. Software developer guide is included too.About Evatronix
Evatronix S.A., headquartered in Bielsko-Biala, Poland, provides IP cores & electronic design services. Main development center of the company is located in Gliwice, close to Silesian University of Technology. Graduates of this University form a core of the company 45-people engineering team. Evatronix IP cores are available world wide through the distribution network of its strategic partner CAST, Inc. (www.cast-inc.com). In European Union countries (except for UK) a parallel sales channel is managed directly by Evatronix. Evatronix is a member of numerous partner programs and associations like: Altera Consultants Alliance Program, Xilinx Alliance Program and SignOnce programs, European Electronic Chips & Systems Design Initiative, Design & Reuse Partner Program, OCP International Partnership, USB Implementers Forum, Inc. More information on Evatronix can be found on the company web site at http://www.evatronix.pl