New Release Simplifies Partial Reconfiguration and Adds New Productivity-Features to Accelerate Design Closure
SAN JOSE, Calif., Feb. 6, 2006 -- Xilinx, Inc. today announced immediate availability of the latest version of its PlanAhead(TM) software, a hierarchical design and analysis solution that along with Xilinx ISE(TM) software delivers a two speed-grade performance advantage for Xilinx Virtex-4(TM) and Spartan(TM)-3 FPGAs over competing offerings. The new release also enables significant savings in cost, size and power consumption by simplifying partial reconfiguration for Xilinx FPGAs. Additional PlanAhead 8.1 productivity enhancements include the ExploreAhead feature, which allows designers to employ multiple design strategies to meet their timing goals in the shortest possible time.
"Many FPGA design teams tell us they are willing to integrate a new tool into their design flow if it helps them meet their timing targets with greater certainty in a shorter time," said Bruce Talley, vice president of the Design Software Division at Xilinx. "They want a tighter correlation between logic and physical domains, and help in automating design iterations. PlanAhead 8.1 builds on the capabilities of our ISE Fmax Technology and demonstrates that a little additional time spent interacting with one's design pays big benefits in performance, functionality and cost."
Optimized Hierarchical Design Delivers Unprecedented Performance Gains
Nominated as a finalist in the 2006 DesignVision awards, PlanAhead streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. The tool allows designers to utilize a hierarchical design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options. Recent customer benchmarks yielded average Fmax performance improvements of 30 percent relative to competing FPGAs, which translates to an average of two speed-grade performance and cost advantage for customers. Complex, multi-clock, high-utilization designs yielded improvements of 56 percent on average over competing solutions.
"PlanAhead has enabled us to realize significant performance improvements in a very short time," said Todd Cicchi, design engineer, Nova Sensors, a developer of image sensors and image processors. "PlanAhead provides a unique solution to our design problems, filling a long-empty hole in the FPGA design methodology."
Simplified Partial Reconfiguration Reduces Size, Weight, Cost and Power
PlanAhead 8.1 software introduces new features and capabilities that streamline the partial reconfiguration design flow. Partial reconfiguration allows customers to save on device count, size, power and cost by allowing predefined portions of an FPGA to be reconfigured while the remainder of the device continues to operate. The new release simplifies the creation of dynamic modules and allows customers to create multiple floorplans for each of their design implementations.
Specifically, PlanAhead 8.1 enhancements offer additional design rule checking, overlap detection, automatic macro creation for module-to-module IO, and a new place-and-route wizard. PlanAhead also controls and manages these implementations in ISE in a simple and easy to use design environment. These improvements make partial reconfiguration more accessible for a wider range of applications, including automotive control functions and software defined radio, where it is already being rapidly adopted. Customers interested in partial reconfiguration support in PlanAhead and ISE should contact their local field application engineer.
"Partial reconfiguration support in Xilinx software and devices will open up new business models for Xilinx and their customers," said Michael Jones, vice president of business development at IBS. "Xilinx has simplified the software methodology for partial reconfiguration by providing an easy-to-implement design flow with its PlanAhead and ISE releases. The new PlanAhead design flow will help enable access to this technology for the company's end markets such as Automotive, Aerospace and Defense."
Productivity Enhancements Accelerate Design Closure
The PlanAhead 8.1 release provides greater levels of automation and a more intuitive graphical interface to dramatically reduce development cycles. The new ExploreAhead feature enables designers and design teams to manage and reuse multiple design strategies while maximizing their computing resources. For example, users can create multiple floorplans, each with its own set of options or strategies and process them in a prioritized manner across multiple processes. This enables customers to achieve their targets in the fastest possible time.
Other productivity enhancements include improvements to the schematic viewer for more efficient and intuitive navigation, design analysis and debug and a graphical representation of design hierarchy for enhanced design exploration.
Pricing and Availability
The PlanAhead 8.1 Design Analysis Tool is available on all major operating systems as an option to Xilinx Integrated Software Environment(TM) (ISE) software. Single-user licenses at $5,995 include training. Customers can try PlanAhead by downloading a free 30-day evaluation at www.xilinx.com/planahead About Xilinx Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.