Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
SANTA CLARA, CA – February 20, 2006 – Tensilica, Inc. today introduced the Diamond Standard 570T processor core, a formidable competitor for the ARM11 processor core. This high-performance 3-issue static superscalar, synthesizable controller core provides more than twice the performance than the ARM1156T2-S in half the area and with less than half of the power.
“The Diamond Standard 570T is ideal for customers who want high performance but are hitting the wall with the ARM11 when it comes to area, performance or power, or where large up-front license fees are a barrier,” stated Steve Roddy, Tensilica’s vice president of marketing.
The Diamond Standard 570T consumes 0.192 mW/MHz in a 130-nanometer LV process and 0.275 mW/MHz in a 130-nanometer G process (all typical conditions). This is much less power than the ARM1156T2-S (.45 mW/MHz) and less than half the power of the ARM1136J-S (.60 mW/MHz) in a 130-nanometer G process.
The performance-leading Diamond Standard 570T has over twice the performance of ARM11-based SOCs and the ARM1026EJ-S core, according to EEMBC benchmarks (see www.eembc.org for full details). The following chart illustrates the comparison, using the Freescale iMX31 as representative of the ARM1136JF-S and normalizing all results on a per-MHz basis.
|1.0 ||1.29 ||2.55 |
|1.0 ||1.47 ||2.91 |
|1.0 ||1.19 ||1.64 |
|1.0 ||1.06 ||2.28 |
|1.0 ||1.24 ||2.30 |
Results normalized on a per-MHz basis
The Diamond 570T is much smaller than the ARM11 processors. Area for the Diamond 570T is 1.46 mm2, while the ARM1156T2-S (2.4 mm2) and ARM1136J-S (2.85 mm2) are much larger. A big part of this size difference is a result of the efficiency of the Diamond 570T, which can reach high performance levels with only a 5-stage pipeline. The ARM1156T2-S has a 9-stage pipeline and the ARM1136J-S has an 8-stage pipeline. Deeper pipelines are less efficient in “instructions per clock” due to higher branch delays and other penalties.
Based on Proven Xtensa ISA
The entire Diamond Standard family is based on Tensilica’s proven Xtensa processor architecture, a post-RISC-style architecture with native 32-bit data types (operands and ALUs) for the baseline 80+ instructions. Compact 24-bit/16-bit instruction encoding reduces power consumption and produces 25to 50 percent smaller code (better code density) than standard 32-bit architectures. Register windows for efficient procedure switches provide high performance with low power. The base Xtensa ISA also provides powerful branch instructions and complex bit manipulations.
VLIW (Very Long Instruction Word) Architecture
The Diamond 570T CPU incorporates Tensilica’s VLIW instruction encoding technology, which enables extremely high instruction throughput per processor cycle. The processor automatically switches between 16, 24, or 64-bit instructions with no manual user mode changes. The 64-bit encoding “bundles” three instructions that are issued simultaneously, allowing performance levels well beyond single-issue machines, while maintaining a much smaller die area than dynamic superscalar processor architectures.
High-Speed, Zero-Latency Streaming-Data Queue Interfaces
The Diamond 570T processor core provides designers with one high-speed 32-bit direct data queue interface and a companion 32-bit direct data queue output interface. Designers can connect these queue interfaces to high-throughput data streams within the SOC. The queues are accessed via special instructions in the Diamond 570T instruction set that completely bypass the traditional Load/Store mechanism and bus of conventional processors. And since these queue instructions can be automatically scheduled and bundled into VLIW bundles by the XCC compiler [see companion news release, Diamond Standard Series Toolset] data intensive computations can proceed with data being consumed or produced through the queue interfaces every cycle. Coupled with computations in the same instruction bundle, the result is both dramatically higher performance and dramatically lower power consumption compared to the same task being run on a conventional single-issue scalar processor with only a traditional system bus interface.
Microcontroller-Style Direct Input Wires and Output Ports Simplify I/O
The Diamond 570T processor core also provides designers with direct interface input ports and output wires for direct connections to other hardware blocks on the chip. These direct interface ports and wires provide a convenient and lower-power alternative compared to using bus-based, memory-mapped I/O interfaces. Thirty-two individually sampled input ports and 32 single-bit output wires provide device-driver programmers with a generous number of general-purpose I/O bits for hardware interface and system control. These wires and ports are similar in function to GPIO pins on classic microcontrollers, and unavailable on the ARM11 processors.
AMBA AHB Interface Available
The Diamond 570T, like all Tensilica Diamond Series cores, is available with either the native Tensilica PIF processor interface, suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect) or with an AMBA AHB-Lite interface. SOC designers therefore can choose any common on-chip bus and leverage existing infrastructure and peripheral component sets.
Tensilica’s new Diamond Standard family of processors is available now, either direct from Tensilica or from a roster of ASIC and foundry partners also announced today. See separate news releases or go to www.tensilica.com for more details.
Tensilica offers the broadest line of processor cores on the market today, with the six new members of the Diamond Standard processor family plus an infinite number of Xtensa configurable processor possibilities for customers requiring optimized, application-specific solutions. Tensilica’s low-power, benchmark-proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. Tensilica also provides industry leading automated tool support for its processor families. For more information, visit www.tensilica.com.