NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Toshiba, NEC Electronics and Fujitsu Announce Agreement on ''COSMORAM Rev. 4'' Common Pseudo SRAM Specifications for Mobile Devices
Tokyo, February 15, 2006 – Toshiba Corporation, NEC Electronics Corporation, and Fujitsu Limited today announced that they have reached an agreement on standard interface specifications known as COSMORAM (COmmon Specifications for MObile RAM) Rev. 4, for Pseudo Static Random Access Memory (PSRAM) (*1) for use in mobile devices. Based on these specifications, each of the three companies will independently begin production and sales of PSRAM devices, with products scheduled to be available from each company from March 2007.
The three companies first created common specifications in September 1998 for stacked multi-chip packages (MCPs) that include both Flash memory and SRAM. In March 2002 the companies jointly announced COSMORAM Rev. 1 with page mode specification for PSRAM, followed by the announcement of the addition of burst mode specification for PSRAM in February 2003 (Rev. 2), and additional specifications for burst mode PSRAM in September 2004 (Rev. 3). As a result of these agreements, the three companies share common interface specifications for PSRAM, which easily enables higher speeds and higher densities, and eliminates the need for customers to be concerned for compatibilities among the three companies' PSRAMs.
The new COSMORAM Rev. 4 is a specification for PSRAM with double data rate burst (DDR burst) (*2) mode, which enables up to twice the previous data transfer rates. DDR burst mode enables a tremendous leap in data read/write performance by achieving twice the peak data bandwidth of conventional products. In addition, the short latency mode, which cuts initial access time to roughly half that of conventional products, improves effective bandwidth. These functions are optimal for mobile phones and mobile information terminals, which require ever-increasing levels of high-speed processing.
As with past COSMORAM specifications for PSRAM, customers can continue to standardize design formats, eliminating the need to customize product designs, thereby helping to shorten the design cycle and dramatically improving design efficiency. In addition, since the three companies are using common specifications, they can act as alternative sources for each other, helping to ensure a stable market supply of PSRAMs.
The major areas standardized under COSMORAM Rev. 4 include the following:- | Double Data Rate Burst Mode (*2) |
- | Short Latency Mode |
- | Capacity |
- | Voltage Range |
- | Control Pin Names And Functions |
- | Truth Table (*3) |
- | Mode Register (*4) Setting Method |
- | AC Timing Specifications |
Glossary
(*1) Pseudo SRAM (PSRAM):
An SRAM compatible memory that uses a DRAM cell array for high densities and low bit cost, and that can self-regulate the refresh operations necessary for data memory storage in its internal memory components.
(*2) Double Data Rate:
A method that executes two data transfers per clock cycle synchronizing with two clock signals.
(*3) Truth Table:
A table defining how a device's operations mode correlates to the external signals used to set that mode.
(*4) Mode Register:
An internal register that stores the control code used to govern the device's operating mode, set externally.
All company and product names mentioned herein are trademarks or registered trademarks of their respective owners.
|
Related News
- Toshiba, NEC Electronics, and Fujitsu Agree On "COSMORAM Rev.3" Common Specifications For PSRAM
- NEC Electronics Embeds MoSys' 1T-SRAM Memory Technology in 90nm Custom ASIC; Companies Extend Agreement To Use 1T-SRAM In Upcoming Consumer Applications
- DOCOMO, Renesas Electronics, Fujitsu, NEC, Panasonic Mobile Communications and Sharp to Develop Mobile Application Platform
- NEC Electronics and Wind River Expand Collaboration on Linux Solutions for Portable Audio/Visual Devices Market
- Transmeta Announces That NEC Electronics' M2 Mobile Phone Chip Incorporates LongRun2 Technologies
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |