DALLAS -- February 22, 2006
-- Texas Instruments Incorporated (TI) (NYSE: TXN) today announced the release of version 5 of the Pyramid ASIC Design Kit, targeting telecommunications, consumer and wireless infrastructure markets. The Pyramid Design System is TI's digital design kit, used for internal designs and external ASIC engagements. It leverages TI's state-of-the-art high-performance standard cell libraries in 130nm, 90nm and 65nm technologies, and provides world-class, low-power consumption, area density and operating performance.
With this release, TI announces extended support for commercially-available design synthesis tools. Moving forward, TI now accepts hand-offs generated by Cadence, Magma or Synopsys commercially-available synthesis tools to provide TI customers with the additional flexibility to release netlists generated by their preferred tools.
"TI's customers have always had access to world-class process technologies through our standard cell libraries and design kits," said Steve Sutton, vice president of TI's ASIC business unit. "Our ASIC customers now also have multiple ways to generate and provide us with their netlists, ensuring they can select from among the best EDA solutions when driving entitlement from those TI process technologies. We have seen internal TI design teams make great use of this flexibility, and we are pleased to offer our external customers the same flexibility."
TI is a leader in developing and marketing advanced ASIC semiconductor technology solutions, and supporting customers with its largest and most complex designs. TI leverages its advanced semiconductor process technology, embedded intellectual property (IP) including high performance, lower DSP architectures, advanced packaging and ASIC design kits to meet customer design targets in a variety of end applications.