SAN JOSE, Calif.--Feb. 27, 2006
--Industry leaders, working through the Silicon Design Chain Initiative (SDC), today announced a second, enhanced version of its power-management methodology and implementation up to tapeout of the ARM® 1136JF-S(TM) processor as proof of the methodology and its interdependent technologies. The new methodology is based on ARM IP, the Cadence® Encounter® digital IC design platform, and TSMC's Reference Flow 6.0. The project validated new automated power-shutdown techniques using the ARM Advantage(TM) standard cell library with the ARM Power-Management Kit, which contains new functions that enable advance power savings techniques. The analysis showed a standby leakage power reduction of 98.5 percent for the shutdown sections, compared to the first SDC's power-management methodology without standby capabilities announced in 2005.
Applied Materials, Inc., ARM, Cadence Design Systems, and Taiwan Semiconductor Manufacturing Company (TSMC) form the Silicon Design Chain Initiative.
Managing Power Consumption
The new methodology expands on the techniques announced by the initiative last year by adding enhanced automated methods for dynamic and leakage-power reduction, including power-shutdown techniques, low-power Design-For-Test (DFT) and low-power formal verification working in concert with the ARM Advantage physical IP, including its Power-Management Kit, for the TSMC 90-nanometer G process. These methods are designed to enable designers to balance power and performance in designing system-on-chips (SoCs). By validating these methods in a widely used ARM processor design, the initiative makes it easier for designers to adopt these techniques in their low-power design projects.
"It is no longer sufficient for collaboration to be one-on-one -- it takes a design chain," said Jan Willis, senior vice president of Industry Alliances at Cadence. "Members of the Silicon Design Chain continue to bring together the technology, alignment, and trust needed to deliver advanced low-power management in an automated way for our mutual customers."
New, Automated Techniques for Advanced Low-Power Designs
The second version of the Initiative's power-management design methodology features new power domain-aware capabilities that include power gating for leakage reduction, low-power DFT, low-power formal verification, and top-down multi-voltage synthesis. Cadence Encounter RTL Compiler synthesis and implementation flow eases designers' use of power-gating techniques and automates manual optimization processes to help designers turn around low-power designs much faster. Low-power DFT and ATPG capabilities, within Cadence Encounter Test, help limit power consumption during test application while ensuring comprehensive test coverage across timing fault-sensitive, low-voltage circuitry. Power-saving capabilities minimize overall switching during testing, and support low-power designs by detecting small delay defects often missed in other test schemes.
Reducing the Risk of Adopting New Approaches
As designers adopt new tools and methodologies to address the challenges of low-power design, it is critical that they can verify that low-power circuitry has been implemented correctly. Building on the Initiative's first version of its power management methodology, Cadence Encounter Conformal® Low Power provides a combination of transistor abstraction, equivalency checking, and functional verification technology to verify low-power designs. Transistor and logical analysis capabilities help address issues with leakage. The solution can validate that designers have correctly instantiated isolation cells such as those in the ARM Power Management Kit and that they are in the proper states to control the isolation function. In addition, equivalence-checking capabilities ensure that advanced power-gating techniques do not introduce functional bugs through the implementation flow.
"Power consumption continues to be the most challenging issue for the digital-entertainment and mobile-communications markets," said Neal Carney, vice president of Marketing, Physical IP, ARM. "The solution to this challenge resides with broad cross industry collaboration. The Silicon Design Chain with ARM, TSMC, Cadence and Applied Materials is one of the leading examples of this with collective delivery of a 'proof of concept' that validates methodologies in actual designs."
The Silicon Design Chain's newly expanded power-management methodology is now available through the Initiative's member companies. A white paper about this methodology can be found at http://www.silicondesignchain.org/.
About the Silicon Design Chain Initiative
In today's disaggregated design environment, collaboration is essential for solving nanometer design challenges. Industry leaders Applied Materials, ARM, Cadence Design Systems, and TSMC are working together through the Silicon Design Chain to provide system-on-chip (SoC) design teams with a predictable, repeatable path to silicon success. The foundation of their approach is silicon readiness, which is based on a combination of silicon characterization, silicon-validated IP, design kits and reference flows. Only through collaboration can companies provide customers with a proven path from design to volume production, because no one company can do it alone. For more information, please visit www.silicondesignchain.com.