TOKYO Toshiba Corp. has introduced an 0.18-micron embedded DRAM ASIC process that boasts logic-transistor performance equal to a pure-logic process. At the same time, Toshiba said it has managed to reduce by 20 percent the process steps normally required to merge logic and DRAM processes.
The idea of merging DRAM with logic has long been touted as a way to bolster device performance for parts most in need of fast memory access. The problem has been the trade-offs: Better logic performance frequently comes with lower DRAM density, and often the extra processing steps of adding DRAM have kept manufacturing costs high.
Toshiba, one of the early companies to jump into embedded DRAM, is looking to make the marriage of DRAM and logic a little less painful: Sacrifice some DRAM density, the company says, and we'll give you an embedded DRAM process that matches the performance of pure logic and comes close in the number of process steps.
To put embedded DRAM logic performance on a par with pure logic, Toshiba focused on keeping the two as consistent as possible. At the same time, the company had to come up with a way to get rid of the "salicide" problem. Salicide, short for self-aligned cobalt silicide process step, is necessary for forming low-resistance logic circuits, but it is a killer for DRAM data-retention times.
Crafting an embedded DRAM process that closely resembles pure logic benefits both the ASIC design customer and the chip manufacturer, Toshiba said. For its part, Toshiba can cut back on the number of steps normally needed to merge the two processes and can use similar tools for reactive etching and deposition. Designers also can count on using the same design rules and device parameters rather than having to use separate functional-block libraries.
"From the 0.25-micron generation we were using a DRAM-based technology. However, we can't get compatible ground rules with logic," said Hiroshi Takato, a researcher with Tos hiba's System LSI Division (Yokohama, Japan). "In some cases, we can't use the same IP [intellectual property]. Most of the business is ASIC so we have to provide two libraries to customers one for eDRAM and one for base logic."
Accordingly, Toshiba made sure the PMOS and NMOS structures that make up the CMOS transistors in the new embedded DRAM process look the same as they do in a logic process.
That means using a dual oxide for the polysilicon gate and making sure to cap all the transistor electrodes with silicide. The cobalt silicide is considered a must for logic performance, but it creates a source of leakage for the DRAM cell and creates problems when the refresh cycle is determined.
"We have to introduce the salicide process in order to get low resistance," Takato said. "But if this is done in a DRAM cell we encounter some leakage problems. The DRAM cell is very sensitive to leakage, so we have to be able to keep the charge in the capacitor."
In a normal DRAM process, the polysilicon gate electrode is topped off with a layer of silicon nitride to avoid shorts while the source and drain are given a coating of silicide. But since Toshiba's goal was to match a pure-logic transistor, the company had to find a way to give all three a silicide treatment to maximize performance while keeping leakage in check.
Toshiba's answer was to first widen the space between the bit lines and narrow the space between the gate conductors during the gate formation. The next step was to deposit a sidewall dielectric film that completely fills the narrow region between the gates. The top layer of dielectric is then stripped away using an ion etch process to expose the electrodes for silicide deposition.
Because the space between the gate electrodes is so narrow, the dielectric sidewalls build up into a thick layer during deposition. That protects the n-junction connecting the trench capacitor from leakage-prone silicide, which sits above the thick clump of dielectri c film.
A pure-logic process normally calls for dielectric sidewall formation before the silicide is deposited anyway, so there's nothing really unusual about this so-called self-aligned salicide-blocking step, Takato said.
That essentially leaves only two additional steps over a pure-logic process: digging the deep trench capacitor in the early stage and later creating an NFET array to adjust the threshold voltage.
The main virtue is in the logic performance. After testing the process using NAND and NOR circuits, Toshiba found virtually no difference between pure-logic and embedded DRAM transistor performance. "All circuits showed the same performance," Takato said.
Moreover, because a trench capacitor doesn't need a high-temperature process to form the capacitor as stacked capacitors do, Toshiba is free to use aluminum or copper for the bit line material rather than higher-resistance tungsten. That means the bit line can also serve as the first metal layer, eliminating two mask steps, Taka to said. All told, Toshiba was able to reduce by one-fifth the number of process steps required to merge embedded DRAM and logic, Takato said.
Compared with commodity DRAMs, however, Toshiba's 0.18-micron embedded DRAM process still has a bigger cell size. At 0.45 micron squared, the cell size equals a 10F squared cell, where F denotes the feature size. Today, most commodity DRAM cell sizes are at 8F squared and DRAM companies have been pushing for cell sizes as low as 6F squared for 1-Gbit DRAMs.
Yet the cell size is still several orders of magnitude smaller than standard six-transistor SRAM and appears competitive with other leading ASIC vendors' cell sizes. IBM Microelectronics' 0.17-micron (drawn) SA-27E process, which also uses a logic-based salicide process and trench capacitors, has a DRAM cell size of 0.56 micron squared, according to IBM.
Toshiba expects the new process will woo customers designing devices that need to process large amounts of data at very hi gh speeds. That job can be done much faster using wide on-chip buses connecting logic to DRAM on the same die.
Graphics-processor vendors were early users of embedded DRAM, though more recently the technology has fallen out of favor with some of the larger graphics-chip companies for reasons of cost.
Now, vendors of Gigabit Ethernet controllers are turning to embedded DRAM as a way to quickly cache more incoming packets. Intel Corp.'s Level One Division is among the early adopters.
Toshiba has started sending out samples of the first chips based on its 0.18-micron embedded DRAM process, and plans to move into mass production by the fourth quarter. Right now, the company uses aluminum for the metal layers, but Takato said Toshiba may migrate to copper as a way to use thinner metal and reduce the capacitance.
The move to copper could come next year, when the company plans to shrink the gate length from the current 0.14 micron to 0.11 micron.
Toshiba has touted the trench-capacitor DRAM p rocess as being conducive to embedded DRAM. Takato acknowledged, however, that the company may eventually have to switch to a more conventional stacked-capacitor process as the formation of a trench with bigger aspect ratios becomes more unwieldy.
"The trench-capacitor structure is basically better for embedded DRAM," he said. "But we're not sure we can go to the 0.1-micron process generation using trench. If we come to a limit, [we'll] have to migrate to stacked capacitors."