Faraday Reaffirms Its Commitment to Structured ASIC Business
Unique Product Strategy and Healthy Return on Investment Provide Confidence to Expanding Faraday's Product Portfolio
HSINCHU, Taiwan and SUNNYVALE, Calif. -- April 4, 2006 -- Faraday Technology (TAIEX: 3035), a leading ASIC and IP provider, today announced that it is satisfied with its structured ASIC business, and will more than double its portfolio by the end of 2006. This announcement is in response to questions raised by LSI Logic's exit of its RapidChip Structured ASIC business, and Synplicity's withdrawing its support for Structured ASIC design tools.
"We want our customers and investors to know that we have invested carefully, and is reaping excellent returns on our Structured ASIC product portfolio," said H.P. Lin, President of Faraday Technology. "Our unique vision of reducing ASIC NRE cost instead of replacing high unit price FPGA chips, coupled with our application-focused product lines have helped us avoided the issues that other players have encountered."
Most of the Structured ASIC vendors, including LSI Logic, have fashioned their product lines after embedded arrays of the gate array era, with large product lines of generic blank slices for customers to add their custom logic designs on. The large product line results in huge upfront investment, as well as on-going inventory costs. Furthermore, many of these slices lack the focus to be used by customers who are looking for particular solutions.
Faraday's Structured ASIC Success
Faraday's unique Structured ASIC strategy starts with market focus: PC peripheral and network communication. The PeripheralComposer (PC-1) and NetComposer (NC-1) are optimized for their respective market space: embedded KVM switch, and PCI-X to Gigabit Ethernet traffic. With only 40% of PC-1 and NC-1 being structured ASIC logic, the rest optimized custom ASIC, both products are price competitive against ASSP solutions. To date, Faraday has won ten design wins, and expects about $30 million in production revenue over the lifespan of just these two products.
"Faraday's Structured ASIC platform strategy has been to dominate specific market segments with the smallest die size and fastest turnaround time," said Dr. George Hwang, Vice President of R&D and Marketing at Faraday. "We are very glad the success has given us the confidence to expand our product offering."
Since the Composer product line is meant to be the lower-NRE cost solution to traditional ASICs, the design flow has remain compatible to Synopsys- Cadence mainstream ASIC methodology. Therefore, the Synplicity EDA product line termination will not affect Faraday and its customers at all.
Faraday expects to announce a third product of its Structured ASIC shortly, and will announce the follow-on products for the PC-1 and the NC-1 in the second half of this year.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, USB 2.0, Ethernet, Serial ATA, and PCI-Express. With more than 630 employees and 2005 revenue of $180 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other markets, worldwide. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: http://www.faraday-tech.com
|
Faraday Technology Corp. Hot IP
Related News
- Faraday and MorethanIP Enter Partnership for 10GbE/XAUI & IEEE 1588 Ethernet IP Cores for ASICs and Structured ASIC Engagements
- Faraday and Intelop Enter Partnership for Custom Networking ASIC and Structured ASIC Engagements
- Faraday Expands Structured ASIC Product Line with FIT-18 Template
- Faraday Announces Peppercon as its First PC-1 Structured ASIC Mass Production Customer
- Faraday Contracted Three ASIC Business Agents in Korea to Expand its Global Presence
Breaking News
- Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs
- MIPI Alliance Announces OEM, Expanded Ecosystem Support for MIPI A-PHY Automotive SerDes Specification
- Deeptech Keysom completes a €4M fundraising and deploys the first "no-code" tool dedicated to the design of tailor-made processors
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Faraday and Kiwimoore Succeed in 2.5D Packaging Project for Mass Production
Most Popular
- Deeptech Keysom completes a €4M fundraising and deploys the first “no-code” tool dedicated to the design of tailor-made processors
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Electronic System Design Industry Posts $4.7 Billion in Revenue in Q2 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |