Synopsys offers commercial SystemC simulator

"The significance is that we're completing the flow," said Joachim Kunkel, vice president of Synopsys' system-level design group.

By adding SystemC simulation to its CoCentric System Studio product, Synopsys is removing a major roadblock, Kunkel said. While a free simulation kernel is available at the Open System C Initiative Web site, it's not really production-worthy, he claimed. "There's no design-entry capability, and the debugging is awkward, because you debug C++ rather than SystemC code," he said. "Users wanted a source-code debugger for SystemC."

And that's exactly what the new CoCentric System Studio provides, Kunkel said, along with graphical or textual design entry and a co-simulation capability with Synopsys' VCS Verilog or Scirocco VHDL simulators. Vera testbench support is also available. "It's really a complete simulation environment with all the things you'd expect to be in there," Kunkel said.

Users shouldn't expect a faster simulator, however — Synopsys' offering will run at about the same speed as the free OSCI kernel, for now. "We wanted it to be correct before we started optimizing for speed. It will get faster," Kunkel said.

CoCentric System Studio existed before, but was initially a simulation environment built around Synopsys' Cossap DSP simu lator. Now, Kunkel said, Synopsys is transitioning the tool suite to revolve around SystemC — so far as that is possible. The current SystemC version 2.0 still doesn't support data flow or state-transition diagrams, so those capabilities are still provided by the original Cossap technology.

STMicroelectronics has built a design environment around the forthcoming release of CoCentric System Studio. Marcello Coppola, project leader in ST's advanced systems technology (AST) group, said his company will use the Synopsys technology to upgrade existing tools for ST's proprietary IPsim class library.

"IPsim is a C++ library that provides most SoC modeling concepts. We developed the library to transfer knowledge to the [design] divisions," Coppola said. In the interests of standardization, he said, a lot of the IPsim concepts have been "pushed inside SystemC."

"System Studio provides productivity tools, but we don't lose anything that we had with Ipsim," Coppola said. "System Studio is a way of making people talk to each other with reduced effort."

Coppola's AST group has assembled a large number of bus and core models, including ARM's Amba hardware bus (AHB) and Amba peripheral bus (APB), a variety of generic cores such as interrupt controllers, and a ST100 processor core debugger model. Coppola said the AST group and several universities provided the AHB and APB SystemC models.

According to Coppola, a Sun Ultra 60 was able to achieve simulation speeds of 100 kcycles/second when running these models, rising to more than 400 kcycles/s on an optimized Blade 1000.

Kunkel said the commercial simulator will not be sold separately from System Studio except in the form of server-farm licenses, using a pricing model similar to that used for VCS regression-test environments.

The co-simulation interface supported by the simulator today is based on the programming language interface, but Kunkel said the company aims to move to a direct kernel interface in a later relea se to improve speed with simulators such as VCS.

CoCentric System Studio 2002.05, the release that will contain the SystemC simulator, ships in May starting at $26,950.