Announces Sequence partnership to ensure consistent, significant power improvements
PALO ALTO, Calif. - April 5, 2006 - Arithmatica, Inc., the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, today announced version 3.0 of their CellMath datapath design tools. The milestone release incorporates power-knowledgeable synthesis and an extended Verilog interface capable of specifying robust datapath structures. Arithmatica has also entered into a partnership with Sequence Design to ensure that designers of complex SOCs can use both CellMath, for data path, and PowerTheater, for other blocks and full chip to achieve significant power improvements. Initial users of the new CellMath tools have reported typical ten to twenty percent power reductions in complex datapath circuits. The power optimization features are released for production use and the Verilog interface has been beta-released to current licensees and is expected to be production released this calendar quarter.
New CellMath Designer 3.0 features include:
- Concurrent performance and power optimization with automated architecture and cell selection based on user dynamic and leakage power and timing constraints;
- Verilog input language support including pragmas to explicitly instantiate advanced arithmetic datatypes such as carrysave wires and features such as internal rounding;
- Enhancement of Verilog behavioral output model to improve support of formal verification flows.
10GBASE-T - 10 Gigabit Ethernet over copper - chips represent some of the most sophisticated mixed signal designs in existence. The challenge of error correction over copper at these data rates requires very high performance signal processing and all of this has to be achieved within a power envelope which does not compromise system reliability or robustness. CellMath Designer version 3.0 provides for power optimization through architecture selection - offering lower power in demanding applications like 10GBASE-T.
"The winners in the 10GBASE-T market will be defined by the highest performance and most power efficient designs. Arithmatica's CellMath Designer enabled our team to significantly reduce overall chip power and reduce datapath area while meeting the throughput requirements in our critical signal processing blocks," said Sridhar Begur, Teranetics' Director of ASIC Design. "In addition, the behavioral models provide an elegant way to formally verify the netlist easing the verification bottleneck typical in complex signal processing designs."
Vic Kulkarni, CEO of Sequence Design stated, "We welcome Arithmatica as our newest In-Sequence partner. Our collaboration in low power datapath design will help our common customers, as illustrated by Teranetics' achievement, to differentiate with power-aware designs. Our continuing joint technology in the RTL modeling area will bring improved predictability at the datapath behavioral modeling stage."
Sunil Talwar, Arithmatica's CTO commented, "Both the performance and portable segments are limited by power dissipation. Verilog-driven, power-knowledgeable datapath synthesis provides users another unique degree of freedom - architecture selection - to use in addition to current power management techniques. By incorporating CellMath tools into their flows, datapath designers will gain an incremental 10-20 percent power improvement in addition to their current results."
Pricing and Availability
Arithmatica actively markets and supports its products in North America, Europe, Japan, Korea and Taiwan. The CellMath Designer, Builder and Optimizer tools are term licensed with US single copy annual license fees ranging from $19,000 to $129,000.
Arithmatica is the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, such as those used in 3D graphics, imaging, multimedia, wireline and wireless communications, and embedded processing. Its unique technology, available through its tools products and design services, provides differentiated improvement to licensees' ICs. The company received its first venture funding in 2001 and is headquartered in Warwick, UK, with sales and support operations in Palo Alto, California. For further information about how its silicon math solutions increase silicon efficiency and boost productivity, please visit: www.arithmatica.com.