Algotronix announces NIST certification of its AES IP Core and design-in at Quixant
The G2 AES core is the second generation of Algotronix Advanced Encryption Standard IP and implements the complete functionality of FIPS 197 and SP800-38A. The certification is for all standard key sizes (128, 192 and 256 bits) and modes of operation (ECB, CBC, CFB, OFB and CTR).
The G2 AES core can be targeted at all modern families of FPGA chips from Xilinx, Altera and Actel. It can also be supplied as synthesisable VHDL source code for ASIC designers. The core is highly configurable making use of VHDL generic parameters to allow users to quickly and easily evaluate area, performance and time tradeoffs. The core is normally supplied in source code form allowing customers with particularly sensitive applications to carry out a full security review.
Jon Jayal, Design Engineer at Quixant said “The Algotronix AES IP core is at the heart of the security system in the QX-10 platform. We selected it because it offered an unrivalled level of performance and efficiency. Design integration was assisted by the expert support we received from Algotronix at every stage.”
About Algotronix
Based in Edinburgh, Scotland Algotronix develops and licences a range of encryption and design security intellectual property to customers throughout the world.
See: www.algotronix.com
About Quixant
Quixant designs and manufactures advanced computer electronics designed specifically for the gaming industry. It has headquarters in London, UK for product design and support and manufacturing facilities in Taiwan. See: www.quixant.co.uk
|
Algotronix Ltd. Hot IP
Related News
- AES Encryption IP Cores from CAST Receive NIST Certification
- PUFsecurity Crypto Co-processor PUFiot Passed NIST CAVP Certification
- Lattice MachXO3D Secure Control FPGA Receives Security Certification from NIST
- Microsemi Announces LiteFast Serial Communication Protocol to Reduce Customers' Design-In Efforts and Time to Market
- Microsemi Achieves NIST Certification on EnforcIT Cryptography IP Cores for FPGA and ASIC Designs
Breaking News
- Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs
- MIPI Alliance Announces OEM, Expanded Ecosystem Support for MIPI A-PHY Automotive SerDes Specification
- Deeptech Keysom completes a €4M fundraising and deploys the first "no-code" tool dedicated to the design of tailor-made processors
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Faraday and Kiwimoore Succeed in 2.5D Packaging Project for Mass Production
Most Popular
- Deeptech Keysom completes a €4M fundraising and deploys the first “no-code” tool dedicated to the design of tailor-made processors
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Electronic System Design Industry Posts $4.7 Billion in Revenue in Q2 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |