400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Digital Blocks Announces its ''Try Before You Buy'' IP Core Evaluation Program
Prospective customers can evaluate Digital Blocks VHDL / Verilog IP cores prior to licensing, in a variety of formats.
GLEN ROCK, New Jersey, April 24, 2006 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for embedded processor system designers, today announces the “Try Before You Buy” IP Core Evaluation Program for all product offerings. Prospective customers have one-of-three options to evaluate a Digital Blocks IP Core: (1) Modelsim compiled simulation-only model with testbench; (2) Time-limited hardware model programmed into an FPGA; and (3) Altera OpenCore Model for evaluation within Quartus II or Altera FPGAs.
Currently, prospective customers can evaluate Digital Blocks’ DB8259A Programmable Interrupt Controller, which maintains the original static design of the Intel 8259A and Harris / Intersil 82C59A devices, the DB8259S Programmable Interrupt Controller, which adds a clock for an all synchronous design, and the DB6845 CRT Controller.
For time-limited hardware model evaluation, Digital Blocks supports Actel, Altera, Lattice, Quicklogic, and Xilinx, FPGAs.
Customers interested in evaluating Digital Blocks’ IP should fill out the IP Core Evaluation Request form at Digital Blocks’ web site, www.digitalblocks.com.
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: 1-201-251-1281; Fax: 1-208-379-1012; On the Web at www.digitalblocks.com
|
Digital Blocks Hot IP
Related News
- Actel Lets Customers "Try Before They Buy" with New Web-Based IP Core Evaluation Program
- Scottish initiative adds online 'try-before-buy' cores for IC designs
- Siemens joins Intel Foundry Services' EDA Alliance program
- Digital Blocks Celebrates 14 Years of Offering 82xx Peripheral Replacements
- Actel's CorefIR v4.0 Delivers Configurable Digital Filter Generation for Rtax-DSP with On-Chip Math Blocks
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |