Xpedion Design Systems Introduces Industry's First Transistor-Level Closed Loop PLL Verification Solution

Milpitas, CA (USA) - April 25, 2006 - Xpedion Design Systems, Inc., a provider of next generation RFIC and PLL simulation and verification, today announced the industry's first transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter. This breakthrough allows PLL designers to fully verify their designs prior to silicon to save design spins and reduce time to production.

Phase-locked loops are present in a majority of complex integrated circuits produced today in applications ranging from microprocessors to wireless communications. They also represent one of the most challenging design hurdles to overcome and are often the reason for failing silicon. The capability of GoldenGate to accurately ensure proper PLL operation is an industry breakthrough. Xpedion has developed this technology in conjunction with close partners and has validated through measured silicon.

"We worked with Xpedion to successfully verify simulated results against measured data for our CMOS PLL with over 500 transistors operating at 622 Mhz, including the crystal oscillator and the integer divider," states Pierre Guebels, Vice President of Engineering at Phaselink Corporation. "This capability is a tremendous step forward in successfully verifying PLLs prior to tape-out."

This capability takes advantage of Xpedion's leadership in harmonic-balance capacity, simulation speed and phase-noise analysis. GoldenGate allows designers to view full noise contributions from all contributors, including the crystal oscillator, allowing designers to pinpoint and fix problems. Historically, this is done through an iterative process of respins.

"We are able to address a clear need in the industry to verify proper PLL operation through our advanced capabilities," says George Estep, Director of Applications Engineering at Xpedion. "This capability will save our customers painful design iterations allowing them to get their products to market faster."

Currently, Xpedion is engaging with existing customers on this technology through partnerships and service agreements. For more information, please contact your local Xpedion support.

About GoldenGate

GoldenGate's modern harmonic balance algorithms also allow for enormous post-parasitic extraction netlists to be analyzed without partitioning. Analysis of only part of the RF design can cause chips to fail exacting power, noise and interference specifications post-tapeout. Xpedion simulations provide designers with the confidence they need to build prototypes, and know they will function inside their spectral masks and meet high yield expectations. Voltage Controlled Oscillator (VCO) Phase Noise and Startup analyses are also key areas where GoldenGate will contribute to ACCO's success-model, capacity and performance expectations.

"ACCO was very aggressive in testing our tool's capability. We were pleased to be able to meet their use-model, capacity and performance expectations." Said Rick Lazansky, Xpedion EVP Engineering.

About Xpedion Design Systems

Xpedion began operations in 1998 and is focused on delivering a new breed of EDA solutions for use in designing wireless and high-speed digital circuits and systems. The company's tools enable design teams to rapidly develop products for the evolving IEEE 802.11 Wireless LAN and Cellular communication standards as well as highspeed digital circuits (e.g. OC 768) and Phase Locked Loops. Xpedion is a member of the Cadence Connections Program, the Synopsys in-Sync™ Program, the Mathworks Partners Program, the Platform Partners Program, and is both a Microsoft and a Sun Microsystems development partner. Xpedion Design Systems, Inc. is located at 1900 McCarthy Blvd., Suite 210, Milpitas, California, USA, 95035. Telephone: 408/449-4000, FAX: 408/449-4030, email: info@xpedion.com, www.xpedion.com.