Cupertino, Calif. -- May 1, 2006 -- Tarek Verification Systems (Tarek) introduces a highly automated verification IP, PCIE-VR, for ASIC designs containing PCI Express interfaces.
The PCIE-VR supports all the PCI Express standards, 1.0a, 1.1, and the coming Gen2. All PCIE designs, such as root complex, switches, end points, and bridges, are supported at both Register-Transfer Level (RTL) and Electronic System Level (ESL). To integrate a PCIE design, PCIE-VR uses standard interfaces, such as serial, PIPE, 8/10b, and parallel. A compliance test suite that implements the PCIE compliance checklist from PCI-SIG is also included.
Tareks PCIE-VR not only fully models and monitors PCI Express functionality, timing, and protocols but also generates realistic sophisticated concurrent-test scenarios automatically in all the three layers. For the transaction layer verification, PCIE-VR features a multi-threaded traffic generator that greatly simplifies the verification of concurrent access to the designs. For the data link and physical layers, PCIE-VR features powerful randomized state transition loop mechanisms that exhaustively verify the flow control protocol, DLCMSM, and LTSSM.
Tarek Verification Systems was founded in 2004 by industry veterans in the ASIC verification and EDA fields. It researches and develops test case automation solutions and highly automated verification IPs for repeatable on-time first-silicon success. Tarek's innovative technology enables verification engineers as well as designers to create quality and sophisticated tests automatically. For more information, please visit www.tarek.com.