Includes Floating Point Support and C-to-Hardware Acceleration Compiler
San Jose, Calif., May 9, 2006—Altera Corporation (NASDAQ: ALTR) today announced the immediate availability of version 6.0 of the Nios® II embedded processor and the Nios II Embedded Design Suite (EDS). The Nios II EDS now includes 32‑bit, single-precision, IEEE 754-compatible floating-point support and the recently announced Nios II C-to-Hardware Acceleration (C2H) Compiler. Additionally, Altera has updated the Nios II embedded processor to improve designers’ productivity when building multiprocessor systems.
“Both the Nios II C2H Compiler and floating-point support deliver increased performance and flexibility to embedded software developers, amplifying the fundamental time-to-market benefits of the Nios II processor as an FPGA-based computing platform,” said Chris Balough, Altera’s director of software and Nios marketing. “Including these features in version 6.0 of the Nios II processor and EDS extends Altera’s leadership in the embedded systems market.”
Floating-point support is delivered as a set of Nios II custom instructions. Custom instructions off-load software operations into hardware and provide an extremely flexible option for increasing CPU performance. When selected by the user, the prebuilt floating-point custom instructions are added into the CPU data path automatically, and all subsequent floating-point operations are evaluated using the dedicated hardware. Fully supported within the software-programming tool chain, floating-point custom instructions offer a completely transparent programming model to the designer.
The Nios II C2H Compiler is a productivity tool for Nios II users. It can substantially increase embedded software performance, automatically converting performance-critical C language subroutines into hardware accelerators and integrating them into FPGA-based Nios II subsystems.
In addition to the tool chain enhancements, the Nios II processor now includes top-level synchronization signals to give designers more flexibility in managing multiprocessor system “bring-up.” Designers now have an option of using a processor-only reset signal to control the order in which the Nios II processors boot.
About the Nios II Embedded Design Suite
The Nios II EDS provides designers with the software tools, utilities, libraries and drivers necessary to develop complete Nios II embedded systems in Altera® FPGAs. The Nios II EDS includes the Eclipse-based Nios II IDE—the cockpit for all software development tasks—including: editing, compiling, debugging, profiling and programming. The Nios II IDE also includes an integrated plug-in for the Nios II C2H Compiler, which is licensed separately.
Pricing and Availability
All active Nios II subscribers will automatically receive the version 6.0 upgrades of the Nios II processor and the Nios II EDS. They will also have access to a free evaluation license for the Nios II C2H Compiler. An annual Nios II subscription may be purchased for as little as $495. The Nios II C2H Compiler is delivered as an integrated plug-in to the Nios II IDE, and is licensed separately for $2,995 per seat.
About the Nios II Embedded Processor
The Nios II soft embedded processor is a general-purpose 32-bit RISC CPU optimized for programmable logic and system-on-a-programmable-chip (SOPC) integration. With over 15,000 development kits sold worldwide and the world’s top 20 OEMs already using the Nios II processor, the Nios architecture is the most popular configurable soft processor available today. For more information, visit www.altera.com/nios2.
Altera’s programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate, and win in their markets. Find out more at www.altera.com.