WALTHAM, Mass.--May 11, 2006-
-Bluespec Inc. today released the latest version of its electronic system level (ESL) Synthesis software, offering a practical delivery vehicle for intellectual property (IP) vendors and improved Verilog register transfer level (RTL) output for debug and verification.
"Our goal with this release was to improve the readability of RTL code and we've succeeded," says Sathyam Pattanam, Bluespec's vice president of engineering. "Designers are concerned about the readability of the output from a high-level synthesis tool. Our new release will change their way of thinking because of the structure, organization, formatting and user control over the RTL code."
This version of Bluespec ESL Synthesis was designed to generate easy-to-follow, readable RTL code that can be used for verification, debugging or as the delivery vehicle for IP. Previously, Bluespec-generated Verilog was used primarily as input into downstream RTL synthesis tools.
RTL enhancements include improved structure and organization of the output. Design elements and comments are organized into clear groupings -- module header, interfaces, state elements and scheduling, for example. Additionally, RTL signals and wires correspond to some variables. Ports are grouped according to the interface methods from where they originate. Each rule and interface method logic is individually grouped and commented. In addition to comments provided by the compiler, comments in the source code, including those for module headers, rules and state element and module instantiations, are included in the generated RTL code at appropriate locations.
This latest release of Bluespec ESL Synthesis offers IP vendors a viable delivery vehicle of RTL code generated from high-level models. Remarks Pattanam: "Comprehending another designer's RTL code can be a serious challenge. Successfully implementing a change, and doing it without an error, is even harder. To succeed, designers must work through another designer's RTL code, familiarize themselves with the design style, catch coding subtleties and fully understand the architecture and micro-architecture; no small task with low-level RTL code. In contrast, Bluespec's source is a terrific specification and the generated RTL is consistent and easy to follow."
Bluespec's powerful parameterization enables configuration of IP for highly customized end-user versions of the output RTL code.
Users control the naming, inlining of various constructs, changes in module hierarchy, inclusion of debug signals, initialization conditions as well as directives for simulation output to give them flexibility in generating RTL code for various uses.
Since the source Bluespec Verilog (BSV) reads like an executable spec, IP vendors can choose to deliver it as such with the accompanying RTL code.
The latest version of Bluespec's ESL Synthesis is shipping today and supports Linux operating systems.
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolset, the only one focused on control and complex datapaths, allows ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling (781) 250-2200.