MOUNTAIN VIEW, California -- May 15, 2006 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced the availability of the ARM-Synopsys Galaxy(TM) Reference Methodology (RM) with support for Synopsys' Design Compiler(R) topographical technology. Design Compiler's topographical technology accurately predicts post-layout timing and area in synthesis, helping eliminate costly iterations between synthesis and layout and enabling faster time-to-market. With the enhanced ARM-Synopsys RM, based on Synopsys' Galaxy Design Platform, ARM(R) Partners can achieve higher designer productivity and reduce overall design time for the wide range of synthesizable ARM processors, including the new Cortex(TM)-R4 processor targeted at the embedded market.
"ARM Partners are continuously seeking ways to get to volume production faster. Utilizing Synopsys' topographical technology helps designers achieve a useful boost in productivity," said Keith Clarke, vice president of technical marketing at ARM. "The results generated by Design Compiler topographical technology have consistently correlated within five percent of post-layout timing and area on multiple processor cores, including the Cortex-R4 processor. Since Design Compiler topographical technology is included in the Galaxy Design Platform, it was very easy to integrate into our ARM-Synopsys Galaxy Reference Methodology."
Topographical technology gives RTL designers early visibility into post-layout design issues and allows them to address them while still in synthesis. It utilizes Synopsys' advanced physical implementation technologies to drive accurate timing and area prediction within the synthesis engine. As a result, RTL designers can eliminate costly iterations between synthesis and layout and generate a better start point for physical design to significantly reduce design time.
The ARM-Synopsys Galaxy RM, co-developed by ARM and Synopsys Professional Services and validated using ARM Artisan(R) Physical IP, offers methodology, documentation on best practices, and optimized scripts that leverage Synopsys' topographical technology, as well as many other new enhancements in the Galaxy 2005.09 release. Using the RM "out-of-the-box," ARM Partners can quickly and easily configure, implement, and verify synthesizable ARM processors to their chosen process technologies. In addition, with the ARM-Synopsys Galaxy RM, ARM Partners can produce highly accurate processor models for SoC integration.
"In today's competitive environment, designers are constantly pushing to reduce time-to-market," noted Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "ARM has incorporated support for Design Compiler topographical technology in its latest Galaxy platform-based ARM-Synopsys Reference Methodology to enable our mutual customers to accelerate time-to-market through a highly predictable, convergent path from RTL to GDSII."
The new ARM-Synopsys Galaxy RM incorporating Design Compiler topographical technology is available starting this month for Cortex-R4 Partners. Topographical technology-based RMs for the ARM926EJ-S(TM) processor, the ARM1176JZ(F)-S(TM) processor, and the Cortex-M3 processor is expected to be available in June, with additional processor support expected during the second half of 2006.
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com.