Company Provides Formal Verification Proof Kit and Methodology for Verifying Designs Containing OCP Interfaces MOUNTAIN VIEW, Calif.--May 18, 2006
--Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced that it has joined the Open Core Protocol International Partnership (OCP-IP), as well as the availability of an Open Core Protocol (OCP) formal verification proof kit as a part of its Formal Testplanner(TM) verification IP knowledgebase. Engineering teams wishing to ensure correct implementation of the OCP can use the proof kit with JasperGold® Express Verification System to formally verify correctness within their design, both quickly and completely. As with other standard protocols covered within Formal Testplanner, the OCP proof kit includes an overview of the protocol, a formal test plan and English description of all protocol requirements, Verilog and VHDL versions of all assertions for the protocol, and a verification strategy.
"We developed the OCP proof kit by working with one of our key customers, who happens to be one of the largest users of the OCP in the world," said Craig Cochran, vice president of marketing at Jasper. "By joining OCP-IP, we can offer the strength of ensuring correct use of OCP under all possible usage scenarios to all customers. When combined with our unique end-to-end data integrity verification capability, the solution offers unparalleled capability to completely prove the correct transport of data."
"OCP-IP addresses problems relating to design, verification, and testing which are common to IP core reuse in plug and play SoC products," said Ian Mackintosh, president of OCP-IP. "Jasper's full formal verification of the OCP 2.1 interface socket via JasperGold Express and the OCP proof kit is a very important addition that provides our members assurance of compliance with the standard."
About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company's flagship product, JasperGold® Verification System, is the first verification product to deliver systematic complete verification, and accomplishes this task within predictable, finite schedule constraints. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to achieve complete verification, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.