Cadence X Architecture Validated for 65-nm Nexsys(SM) Process
HSINCHU, TAIWAN and SAN JOSE, CA -- 05/25/2006 -- Taiwan Semiconductor Manufacturing Company and Cadence Design Systems, Inc. today announced that the Cadence® X Architecture has been validated for TSMC's 65-nm Nexsys(SM) process.
TSMC is now providing 65-nm X Architecture design rules that allow customers to achieve lower cost, higher performance, and lower power designs. In 2005, TSMC became the first foundry to produce an X Architecture device, a PCI-Express graphics processor from ATI Technologies, Inc. TSMC is now production-ready for 0.13-micron, 0.11-micron, 90-nm and 65-nm X Architecture designs. Cadence and TSMC are engaging with mutual customers towards X Architecture production designs at 65 nm.
"TSMC and Cadence have engaged with multiple customers for 0.13-micron, 0.11-micron and 90-nm X Architecture production designs, and are now working with early customers targeting our 65-nm process. The X Architecture provides another dimension to bring cost, performance and power benefits," said Ed Wan, senior director of TSMC's design services marketing.
"Leading design companies around the world are beginning to enjoy the tremendous benefits that TSMC's 65-nm Nexsys(SM) process offers," said Kalyan Thumaty, vice president and general manager of X Architecture at Cadence. "Combining TSMC's advanced 65-nm process technologies with the Cadence X Architecture provides fabless companies an obvious choice to tackle the cost, performance and power challenges of today's demanding marketplace."
The Cadence X Architecture is now available to customers for TSMC's 0.13-micron, 0.11-micron, 90-nm and 65-nm processes.
About the X Architecture
The X Architecture represents an innovative approach for orienting a chip's microscopic interconnect wires, with the pervasive use of diagonal routes in addition to traditional right-angle "Manhattan" routing. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.