Encounter RTL Compiler Global Synthesis Helps Reduce Area and Improve Performance for DDR DRAM Controller Designs
SAN JOSE, CA--Jun 28, 2006 -- Cadence Design Systems, Inc. and Denali Software, Inc. today announced support for Cadence® Encounter® RTL Compiler global synthesis on Databahn(TM) memory controller products. Encounter RTL Compiler synthesis enables Denali customers to achieve smaller, faster and lower power implementations for Databahn DRAM controller designs.
Denali used a top-down methodology featuring its market-leading Databahn(TM) memory controller IP in conjunction with Encounter RTL Compiler technology. Denali is a member of the Cadence OpenChoice IP program.
DDR memory systems have emerged as a critical design requirement for enabling high performance in virtually all electronics products, including everything from cell phones to set top boxes. DRAM memory systems require specialized tuning and tailoring to achieve specific performance requirements for each unique design or application. The Databahn memory controller uses simple synthesis script modifications combined with Encounter RTL Compiler multi-objective optimization to achieve significant advantages in area, speed and performance.
"Systems today demand high performance DDR memory controllers, and designers implementing these controllers require state-of-the-art synthesis tools. We are excited to enable our customers with synthesis solutions from Cadence," said Brian Gardner, vice president of IP products at Denali. "What impressed us most about Encounter RTL Compiler global synthesis is that it was easy to set up and use, and it worked perfectly out of the box. Databahn customers using Encounter now have access to an optimal synthesis solution that provides excellent power-vs.-area tradeoffs for SoC design."
Encounter RTL Compiler global synthesis, a key technology of the Cadence Encounter digital IC design platform, improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route. Cadence defines this metric as quality of silicon (QoS). This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs.
"Denali is the leading design and verification solution provider for standard interfaces, and we are extremely happy that Encounter RTL Compiler has helped to optimize customer implementations of Denali's Databahn memory controller cores," said Dr. Chi-Ping Hsu, corporate vice president at Cadence. "This is yet another example of Cadence's successful IP strategy with an important IP partner. Encounter RTL Compiler synthesis is employed by companies worldwide to create smaller, faster, lower power, and higher quality designs to address the challenges of today's competitive markets."
About Databahn IP Products
Licensed for use in more than 170 chip designs, Databahn is the most trusted design IP solution for standard interfaces, including DDR, Flash, and PCI Express. Databahn IP cores offer configurability and programmability to deliver optimal performance for a wide range of end applications. Databahn is silicon proven in more than 65 chips, spanning 18 process nodes. More information about Databahn is available online at: http://www.denali.com/databahn
About Denali Software
Denali Software, Inc. is the world's leading provider of Electronic Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's Databahn(TM) products support key SoC interfaces including DRAM, Flash, and PCI Express technology. Spectra(TM) is a robust flash file system for NAND flash systems. PureSpec(TM) and MMAV(TM) verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's Blueprint(TM) SystemRDL compiler provides a complete solution for on-chip register specification and management. For more information, visit Denali at http://www.denali.com, call (650) 461-7200 or email email@example.com.
About Cadence OpenChoice Program
The Cadence OpenChoice program enables interoperability and facilitates open collaboration with leading IP providers to build, validate, and deliver accurate models for Cadence design and verification solutions. The program aims to ensure IP quality, integration, and provides engineers access to a broad IP offering through a complete IP catalog. This optimizes the electronics design chain and accelerates customer time to market.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.