ViASIC Introduces Industry's First Two-Mask Standard Metal Fabric for Re-configurable SOC Design; DuoMask Patented Technology Provides a Complete Solution for All Processes
RESEARCH TRIANGLE PARK, N.C.--June 30, 2006--ViASIC, Inc., the leading provider of standard-metal technologies, today announced DuoMask, a high-density, high performance two-layer standard-metal fabric for building configurable SOC's. With DuoMask, designers can easily and quickly use configurable logic to add or change SOC features, fix even minor bugs, and design different versions of the same system for different markets.
For seven metal processes DuoMask uses via layers 2 and 4 to program the pre-built and pre-characterized logic and routing. The configurable logic is built upon existing technologies providing an accurate, proven fabric almost immediately for any process. The new configurable logic libraries require no logic cell layout, timing or power characterization; instead they rely on dependable, proven existing libraries. DuoMask is the densest standard-metal fabric available with 150 gates per mm2 at 90nm.
"DuoMask provides affordable two mask customization for every digital process," said Bill Cox, CTO, ViASIC. "We are excited to provide this new technology which supports virtually anyone, in any process, at any fab and best of all it relies on existing proven and characterized libraries."
Configurable fabrics are one method that SoC designers can leverage their IP with low-cost, low-risk respins that empower customization of existing designs and rapid, easy addition of new features, expanding available markets for this IP. Configurable SoC's use standard-cell flows to build the majority of the chip. Implementing the proven, stable blocks with classic methodologies, only a portion of the chip is built with a configurable fabric. This configurable portion of the SoC can then be used to implement a variety of functions that could be subject to change. With SoC configurability, designers can now get initial versions of a product out before final specs are set, getting hot products to market first.
DuoMask, along with ViASIC's one-mask library ViaMask, and ViaPath, a place and route tool for standard-metal, will be demonstrated at the Design Automation Conference in San Francisco on July 24 at booth 1108. To set up a private suite appointment email dac@viasic.com. For more information on the conference visit www.dac.com.
Price and Availability
DuoMask is immediately available for all digital processes between .35 micron and .45 nanometers. U.S. pricing starts at $95,000.
About ViASIC
ViASIC is a privately held EDA company and the leading provider of standard-metal tools and methodologies. The company's patented ViaMask fabric is a complete library for building platform ASICs or embedding single via layer configurable sections into a system on a chip (SoC). DuoMask is two vias layer configurable fabric built upon existing technologies. ViASIC also offers ViaPath, a robust physical design solution for via-configurable fabrics. ViASIC is located at 6015 Fayetteville Road Suite 214 , Durham, NC 27713. Telephone 919-405-1345, www.viasic.com
|
Related News
- RF Engines to launch dynamically re-configurable radio spectrum channeliser at the ISPC in 2003
- RF Engines launches dynamically re-configurable radio spectrum channeliser
- Intel and Cadence Expand Partnership to Enable Best-in-Class SoC Design on Intel's Advanced Processes
- Flex Logix Joins Intel Foundry Services Accelerator IP Alliance to Enable Fast, Low Power, Reconfigurable SoC's
- AMD Introduces World's Largest FPGA-Based Adaptive SoC for Emulation and Prototyping
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |