TOKYO Drawing on existing IC technology licensing deals, Sanyo Electric Co. Ltd. announced it has designed an ARM-based microcontroller architecture with integrated split-gate flash memory aimed at makers of PC peripherals.
Unlike mask ROM, flash memory is reprogrammable, but the addition of flash to an MCU can be difficult due to process technology differences between the logic and flash memory portions of a chip. Flash also requires rigorous testing, said Toru Akiyama, general manager of Sanyo's MOS LSI division.
The LC67F5000, Sanyo's first device in a planned family, will include 5-Mbits of flash memory based on the split-gate memory cell which Sanyo licensed several years ago from Silicon Storage Technology Inc. (Sunnyvale, Calf.). Sanyo said the split-gate flash should reduce excessive data erase during operation. Though similar in size to a single-transistor stacked gate cell, the split-gate cell is isolated from the bit line to pr event over-erasing during high-voltage operation, according to SST.
The device's MCU is based on the ARM7TDMI core, which Sanyo licensed last year from ARM Ltd. The 3.3-volt chip also includes 256-kbits of SRAM, an 8-bit A/D converter, UART, 16-bit timer and DMA.
Sanyo will introduce variations of the MCU architecture as it ports the design to newer process technologies. The company plans to build the initial devices with a 0.35-micron process technology, and will later migrate to 0.25- and 0.18-micron processes. Sanyo plans future devices that will include 60,000 to 200,000 random logic gates and different configurations of flash and SRAM.
Housed in a TQFP-100 package, the LC67F5000 will be available in sample quantities for about $36 each beginning in October. Volume production is slated to begin next January.