SAN JOSE ( ChipWire) -- Visitors to this week's Network Processors Conference who expect to witness consolidation of the packet-processing industry will instead see two players enter the market from opposite application ends. Both companies, Silicon Access Networks Inc. and SandCraft Inc. are chaired by S3 founder Dado Banatao.
San Jose-based Silicon Access, which has generated a buzz in networking circles by applying embedded memory to packet classification problems, will launch its iFlow Fast Intelligent Router chip set this month. And SandCraft in nearby Santa Clara is a licensee of the Mips Technologies instruction set, which is shifting focus from intellectual property cores to merchant sales of embedded processors for networking applications.
Both companies could step into the market slot of Quantum Effect Devices Inc., which has owned the network-control niche for Mips processors cores. Santa Clara-based Quantum Effect Devices is now being acquired by PMC-Sierra Inc. in Burnaby, British Columbia, which expects to complete its $2.3 billion stock acquisition of the company later this month (see Aug. 1 story).
There is almost no overlap between the business plans of Silicon Access and SandCraft. Silicon Access is pursuingmultichip, multivariate packet analysis for wire-speed support of networks at 10 and 40 Gbits/second, but it's steering clear of control-plane architectures and will instead reference third-party control processors, such as embedded Mips cores. The latter market is where SandCraft hopes to gain adherents to its SR1-GX, a RISC design with vector extensions that was designed for 3-D graphics but is being redeployed for such applications as packet header analysis.
Silicon Access has leveraged its reputation in embedded memory blocks to pull in key designers from IBM Microelectronics, SiTera Inc. and Newbridge Networks Inc. over the past two years, said Rex Naden, senior vice president for marketing and business development. The founders looked at the deep-packet classifier problems being addressed by such companies as Extreme Packet Devices Inc. and initially saw an opportunity to apply a mix of traffic-engineering logic and fast search-engine memory.
"But as we talked to carriers and service providers as well as the equipment OEMs, we realized that more than a classifier was needed," Naden said. "We needed a flexible, expandable chip set for terabit-wire-speed routing, and the design space ended up growing to six chips."
Two of the chips are somewhat traditional packet processors: the iPP packet processor, with eight RISC cores at 266 MHz, and the iTM traffic manager, using 64,000 queues and a full gamut of algorithms - such as weighted fair queuing and weighted round robin -- to organize packets.
Three of the devices perform unique coprocessing duties for 10- and 40-Gbit/second network s: the iAP address processor, handling routing lookup duties such as classless interdomain routing and longest prefix match; the iCL classifier processor, which handles header classification, such as differentiated services code points, with the assistance of 4.5 Mbits of integrated ternary content-addressable memory (CAM); and the iAC accountant, which has more than 2 million counters to gather packet statistics.
Silicon Access considers its primary market the terabit regional WAN edge routers that populated the shared Internet-service-provider centers colloquially known as peering hotels, where the need is great for packet prioritization and scheduling.
The number of customers for iFlow could be small, Naden said, adding, "We're in this business to serve not 15 or 20 startups but the top few vendors that matter."
As a result, he said, in the planning stages of the strategy Silicon Access talked to carriers and service providers as well as router manufacturers.
The patented embedded memory blocks for DRAM, SRAM and ternary CAM were key to implementing complex processors and search engines in reasonably sized dice, though the chips are in no sense small. Silicon Access designs are implemented in a 0.0218-micron process, with 31 mask layers, from Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC).
Silicon Access' Ottawa-based software group, led by a developer from ObjectTime, has produced rich libraries for the processors that include classifiers, policing mechanisms and egress algorithms for iPP, as well as queue and packet transform routines for iTM. Patented technology minimizes code space.
The iFlow family will move into production between the first quarter of 2001 and the first quarter of 2002.
Sandcraft, meanwhile, is carefully planning its own merchant offerings of vertical-market control processors while avoiding disputes with current core licensees NEC Electronics Inc. and LSI Logic Corp. Marketing vice president Michael Barar said the company has focused solely on 64-bit designs and that the NEC VR4300, based on Sandcraft's core, forms the heart of a powerful set-top box from General Instrument Corp. and Motorola Inc.
Sandcraft is exploring how its vector instruction set and MediaLink bus could be augmented with special peripherals for fast I/O throughput. While Barar did not want to specify network processing as the primary target, the tasks described for a high-throughput engine would fit the former QED's model of playing host to switch and router designs.
"Our license with Mips is one of the most far-reaching in existence, which gives us the flexibility of continuing to offer cores on a case-by-case basis," Barar said. "At the same time, we have the ability to sell optimized processors and ASSPs directly to the customer."
Analysts agreed that the move allows Sandcraft to expand its role. "They identified some applications for the technology that they wanted to go after with application- specific standard products," said analyst Jim Hines of Gartner Group Dataquest. "It made sense to do that going with the fabless model."
Perhaps more important, the shift to a fabless model is "certainly going to make them more visible," said Tony Massamini, processor analyst with Semico Research Corp. (Phoenix).
By decoupling from the foundries of NEC and LSI Logic, Sandcraft is free to seek out advanced CMOS processes, including those with copper interconnect. It plans to move its processors from 0.18 to 0.15 micron and eventually to 0.13 micron.
While most packet-forwarding duties do not require use of a floating-point unit, Barar said that Sandcraft's FPU "is efficient enough that it does not represent a significant area. We were somewhat surprised when we developed one design with the floating-point unit off, and customers asked us to put it back on."
The real power of the architectures for networking, however, lies in its heavy pipelining (11 stages) and a speculative execution meth od that offers branch prediction accuracy of 97-98%.
Barar claimed Sandcraft's biggest competitor in embedded markets will be the PowerPC, since "by the time PMC-Sierra acquired them, QED already seemed to be losing some ground" to the PowerPC architecture.
--Additional reporting by Craig Matsumoto