AUSTIN, Texas Alchemy Semiconductor Inc. here is approaching the end of the development cycle of a MIPS-based design that targets Internet edge processing.
The Au1000 is being developed by a team of processor designers led by Rich Witek and Greg Hoeppner. Those same engineers, who have been working together for over a decade, developed the first StrongARM processor while at Digital Equipment Corp.'s design center in Austin.
The 20-member group left Digital Equipment's semiconductor operation after it was sold to Intel Corp. and formed Alchemy following a brief stopover at Cadence.
Alchemy has switched from StrongARM to the 32-bit MIPS architecture, but the goal remains the same: to deliver high performance at relatively low power. Hoeppner said Alchemy will deliver several different speeds of the Au1000. Those speeds will range from 200 MHz at 1.2 volts; 400 MHz at 1.5 V and 500 milliwatts of power consumption; and up to 500 MHz at 1.8 V and 900 mW of power. The 400-MHz part is expected to run cool enough for use in handheld systems.
Alchemy's starting point is a custom design based on the MIPS 32-bit instruction set, but portable enough so that it can be fabbed at three major foundries: Taiwan Semiconductor Manufacturing Co. in Taiwan, Chartered Semiconductor in Singapore and IBM in Burlington, Vt. The first products are expected from TSMC's 0.18-micron LP (low-power) process in the fourth quarter.
Alchemy's first product will fit well with the coming wave of "portable browsers," third-generation cellular phones and voice-over-Internet Protocol phones, although Broockman said they "are still a couple of years away" from high volumes.
"In the meantime, we still have to eat," he said, and pointed to the line-card market as an immediate opportunity for volume sales. Packing more ports in a smaller card cage plays into Alchemy's strengths in power consumption, he said.
The Au1000 is describe d as a system-on-chip, or platform that incorporates peripheral circuits that might have otherwise required four or five discrete devices. And while the team designed the critical blocks using its own set of primitives or cells, many of the peripheral cores were purchased from commercial intellectual-property (IP) vendors.
The two 10/100 Ethernet ports and the UART were licensed from inSilicon (the former IP arm of Phoenix Technologies), while PalmChip contributed gated clock circuits and several cores.
"We spent a fair amount of effort integrating those cores, but Alchemy may be the first company to build something of this complexity with large amounts of commercial IP," said Broockman, who earlier ran the Crystal Semiconductor operation at Cirrus Logic.
How does a design team keep power consumption low in a design that uses considerable amounts of imported IP that is intended to run on multiple foundry processes?
Hoeppner said people mistakenly think that the StrongARM was optimized, down to the last fingernail, to run on the Digital 0.35-micron process at Hudson, Mass. Even with the StrongARM, "We didn't push it as far as we could go," he said, and enough design latitude was included to make the design somewhat portable.
Witek, the chief technology officer at Alchemy, said, "At the 0.18-micron level, the transistors from the three foundries we are working with are not all that different. You do have to give up a little bit on area to make the design portable. The poly spacing rules differ, and so you make that rule a larger space. You give up a little bit of area, it runs a little bit slower, with a little more capacitance" than a custom design targeted at one process. But not much, he concluded.
"This is not a standalone processor; it is an integrated design aimed at the edge of the Internet. We spent a lot of effort on the system architecture, the busing, and did a fairly quick turn in integrating the peripherals because our bus is something that will make it easy to interconnect. That part is a hard macro that we worked hard on."
Hoeppner said, "The way we do design is to create an extremely fast design and then lower the voltage to run the same circuits at low power consumption. We don't use any truly dynamic logic, but we do use circuit techniques, which are pseudo-static, and then put those in a competitive CMOS process. There are things we do to stop the clocks or to operate at low frequency, things that you might not be able to do in a truly dynamic design."
Hoeppner and Witek claim that accumulated knowledge is the key to a successful design. By applying techniques first used on the Alpha, then the StrongARM, and now the MIPS-based design, hundreds of the same optimization techniques can be applied.
"The same group of people have been together, basically, since 1988 or '89," Hoeppner said. He added that "Even though the MIPS architecture is new to us, we are applying solutions that are familiar to us."
Witek said, "This is not a standard c ell design. Though we support a certain level of fab portability, the amount of optimization is still quite large."