Advanced Timing and Power Analysis Features Improve Flexibility, Efficiency and Reliability while Maximizing Performance and Minimizing Costs
MOUNTAIN VIEW, Calif. -- July 10, 2006 -- Actel Corporation (Nasdaq: ACTL) today introduced the latest version of the Actel Libero(TM) Integrated Design Environment (IDE) with new features intended to increase the flexibility, efficiency and performance of designs based on the company's field-programmable gate arrays (FPGAs). With the enhanced SmartGen, SmartTime and SmartPower tools, the Libero IDE 7.2 offers new capabilities for intellectual property (IP) generation to support the Actel Fusion(TM) Programmable System Chip (PSC) offerings. It also offers advanced timing and power analysis functionalities for designers using the Actel Fusion, ProASIC3 and RTAX-S families.
"As more system engineers turn to FPGAs, the Libero IDE 7.2 allows these designers to leverage the capabilities of the Fusion platform whether they are coming from an SoC, mixed-signal, discrete or analog design environment," said Jake Chuang, senior director, application solutions marketing at Actel. "Delivering on Actel's commitment to deliver tools to increase designer efficiency and FPGA device performance, the comprehensive IDE, with its new SmartGen, SmartTime and SmartPower features, now also enables designers to meet their design requirements while lowering costs and improving the reliability of their complete system. "
Smart Tools Aid FPGA Design
For a large variety of commonly used IP functions, the SmartGen tool provides users with design automation functionality to import existing cores and create new ones for their Fusion-based designs. New features include a sample sequencer, a sample sequence configurator and a visual phase-locked loop (PLL) configurator. Further, the state management capability that audits module changes and dependencies can now pass this information directly to Libero, allowing the designer to update all dependent modules with one click. In addition, SmartGen now supports the direct update of nonvolatile memory for analog system blocks, thereby reducing or eliminating lengthy iterations through synthesis.
Actel's SmartTime feature provides static timing analysis capabilities based on industry standards, such as Synopsys Design Constraints (SDC), as well as new visual constraint dialogs, thereby easing the transition from ASICs to mixed-signal FPGAs. Clock-source latency analysis, which allows the definition of a clock constraint for clock jitter, is another new feature to help designers analyze FPGA timing in the context of its surrounding environment. SmartTime also supports recovery and removal checks for proper timing of asynchronous signals for both internally and externally generated clocks.
Enhancements to Actel's SmartPower power analysis tool, enables users to perform detailed power-consumption analysis, helping to conserve power, cut costs and improve design reliability. SmartPower is now able to generate power consumption information for nets, gates, I/O, RAM, FIFOs and clocks or alternatively, block-by-block by component type. The tool performs rail checks and collates power for all defined voltages. Further, SmartPower supports an enable-rate specifier capability for the per-load estimation of time and active output drives, offering designers the ability to achieve more accurate system power calculations.
The Actel Libero IDE 7.2 Platinum edition is available on Windows and Unix platforms for $2495 and $4995, respectively. The enhanced Libero IDE Gold edition is available for free on Windows. All editions are one-year renewable licenses. For further information about pricing and availability, please contact Actel.
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit www.actel.com. Telephone: 888-99-ACTEL (992-2835).