Avery Design and ASIC Architect Team to Deliver Serial ATA (SATA) IP Solution

ANDOVER, Mass.--July 25, 2006--Avery Design Systems and ASIC Architect today announced a cooperative effort to deliver a comprehensive Serial ATA (SATA) design and verification IP solution.

"Avery is excited to team with ASIC Architect to promote a cohesive design IP and core-to-chip-level verification solution for our customers," said Chilai Huang, president of Avery Design. "Working with IP vendors is a cornerstone in Avery's ability to continue to offer leading edge, comprehensive verification solutions. Our customers will benefit by ASIC Architect and Avery having shared goals and objectives on meeting their needs. Also from a solid core foundation, Avery has been able to build the innovative Serial ATA chip and system level verification features that our customers have come to rely on."

"The complexity of Serial ATA technology, Revision 2.5 and going forward demands a very focused effort in order to provide a complete quality solution to our end customers. ASIC Architect focuses on developing high-quality Serial ATA IP and solutions. Avery's verification framework provides ASIC Architect a solid foundation to develop our SATA IP cores. Avery's comprehensive verification environment and verification test suite has been instrumental in the overall verification of our SATA design IP - both host and device controllers," said Kishore Mishra, president and CEO of ASIC Architect. "Our mutual customers know that their chip and system-level verification is streamlined by leveraging the same robust environment as their core provider."

Under the terms of the agreement, ASIC Architect and Avery will jointly promote their comprehensive solution to end users. Additionally, ASIC Architect has licensed Avery's SATA-Xactor solution to use for internal development.

About SATA-Xactor for Serial ATA

The SATA-Xactor for Serial ATA Verification Solution is a complete verification solution consisting of Bus Function Model (BFM), trackers for transaction, link and PHY, specification protocol assertion checking, and compliance test suites and verification frameworks for functional verification of Serial ATA components. The SATA-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their Serial ATA compliant devices. Verification frameworks form complete testbench environments for Host and Device controller designs. Verification engineers just need to replace an Avery BFM with their design and begin running comprehensive verification tests. The SATA-Xactor environment leverages advanced verification techniques of Avery's TestWizard product supporting complex data structures, transaction database, random generation, temporal property checking, and coverage analysis.

Key Features

• Verilog source code format for BFMs and testcases
• Complete set of fully functional PATA, SATA I and SATA II BFMs for Parallel and Serial ATA components: Host and Device
• Specification based compliance testsuites that target high compliance coverage with protocol assertion checking using Avery's comprehensive checklists
• Test are self-checking, portable, and reusable on most types of designs.
• Randomly mix of test sequences and parameters to produce real system scenarios
• Support for serial, 8b-10b, and PHY interfaces as well as AMBA AHB Interface. Smart monitoring / tracking of FIS transaction, Link, and PHY
• Robust BFM API automates sending Transport FIS and Link primitives and controlling automatic BFM device response behaviors and link and device state transitions
• Supports transaction-oriented request-completion and error injection sequences based on address and command type attributes
• Multiple control/observe levels of DUT adaption (integration) with injection of errors and noise at all protocol layers.
• Native programming interfaces for Vera, Specman, SystemVerilog, SystemC, VHDL, C/C++

About ASIC Architect Cores

ASIC Architect offers complete SATA design IP solutions - host and device controllers. The cores have been architected to deliver very high performance with native command queuing and multiple outstanding command processing support. The cores are also programmable and configurable - user configurable number of ports and FIFO depth.

Key Features

• Supports 3.0 Gb/s and 1.5 Gb/s speed
• Compliant with SATA 1.0a and SATA II specifications
• Implements Transport and Link layer functionalities
• Supports OOB signaling
• Supports 8b-10b encoding/decoding, scrambling/de-scrambling
• Supports Elasticity Buffer on RX path
• Supports ATA and ATAPI devices
• Supports configurable number of ports
• Each port supports multiple outstanding commands
• Supports 64-bit addressing (optional)
• Powered Management (partial, slumber)
• Staggered spin-up support
• Hot plug support
• Supports Native Command Queuing
• Supports First Party DMA, DMA and Programmed IO (PIO) modes
• Supports Comma Alignment (Optional)
• Technology Independent Design for ASIC, FPGA
• Excellent Support from Core Integration through Silicon Bring-up

About Serial ATA technology

Parallel ATA is the primary internal storage interconnect for the desktop, connecting the host system to peripherals such as hard drives, optical drives, and removable magnetic media devices. Serial ATA is the next -generation internal storage interconnect, designed to replace parallel ATA technology. Serial ATA is the proactive evolution of the ATA interface from a parallel bus to a serial bus architecture. This architecture overcomes the electrical constraints that are increasing the difficulty of continued speed enhancements for the classic parallel ATA bus. Serial ATA will be introduced at 150Mbytes/sec, with a roadmap already planned to 600Mbytes/sec, supporting up to 10 years of storage evolution based on historical trends. Though Serial ATA will not be able to directly interface with legacy Ultra ATA hardware, it is fully compliant with the ATA protocol and thus is software compatible.

About Avery Design Systems

Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com.

About ASIC Architect

ASIC Architect, Inc. specializes in providing IP Cores, Solutions and Services in PCI Express, DDRI/II, SATA technology for ASIC and FPGA. Additional information about ASIC Architect, Inc is available at http://www.asic-architect.com/