New software release improves performance, accelerates design closure and offers better signal integrity analysis
SAN JOSE, Calif, – August 28, 2006 –Xilinx, Inc. (NASDAQ: XLNX ) today announced immediate availability of the 8.2 version of its PlanAhead™ hierarchical design and analysis software with support for its newest Virtex™-5 LX family of 65nm FPGAs. Used in conjunction with the Xilinx Integrated Software Environment (ISE™) design tools, PlanAhead 8.2 software delivers a two-speed grade performance and cost advantage over competing offerings.
Leveraging the unique advantages of the Virtex-5 LX ExpressFabric™ technology, 550 MHz DSP48E slices, and flexible clock management tiles, PlanAhead 8.2 delivers unprecedented levels of performance. In addition, PlanAhead 8.2 features a robust, accurate signal integrity analysis capability and improved graphical interface that allows designers to rapidly evaluate multiple design implementation strategies to accelerate timing closure.
Enhanced Signal Integrity & Designer Productivity
PlanAhead 8.2 provides functionality to check limits for weighted average simultaneous switching output (WASSO) analysis. This new functionality allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA. As a result, designers can more effectively manage ground bounce on I/O banks for better signal integrity.
PlanAhead 8.2 extends the capabilities of the ExploreAhead design exploration utility to allow users to run multiple implementations with different floorplans of their design to achieve optimal results. These can be queued or optionally run in parallel when multiple processors are available. In addition, the ExploreAhead tool offers improved directory management, process management, and integration with the FPGA bitstream generation application in the ISE environment.
Other PlanAhead 8.2 enhancements include improved management of physical constraints and viewing of the IO pin properties for a much more streamlined design exploration and floorplanning environment.
About Xilinx PlanAhead Software
Xilinx PlanAhead software streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. The tool allows designers to utilize a block-based design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options to avoid problems downstream.
PlanAhead 8.2 is available on all major operating systems as an option to the Xilinx ISE design suite. Single-user licenses start at $5,995 US list and include training. Multiple user licenses and training packages are also available.
About Xilinx Virtex-5 FPGAs
Built upon the industry’s most advanced 65nm triple-oxide technology, breakthrough new ExpressFabric technology and proven ASMBL™ architecture, the Virtex-5 family represents the fifth generation in the award-winning Virtex product line. Key design team innovations in process technology, architecture and product development methodology have led to unprecedented performance and density gains with Virtex-5 FPGAs – at speeds on average 30 percent higher and 65 percent increased capacity over previous generation 90nm FPGAs – while reducing dynamic power consumption by 35 percent, maintaining the same low static power and consuming 45 percent less area. Initial shipments of the Virtex-5 LX Platform began this year with future platforms to follow. For more information visit www.xilinx.com/virtex5.
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.