Leverages IP From Altera and Micron to Shave Weeks off DDR2 Interface Design Time
SAN JOSE, CA -- September 18, 2006 -- Cadence Design Systems, Inc., the leader in global electronic-design innovation, today announced the availability of the Cadence® Allegro® Double Data Rate 2 (DDR2) design-in IP portfolio. This portfolio enables engineers to optimize DDR2 interfaces on printed-circuit boards (PCBs) and expedite the design process.
The DDR2 design-in IP portfolio features a methodology for designing system-level DDR2 memory interfaces, IO models, PCB constraints, and reference design material from leading memory and FPGA suppliers. The initial offering includes a memory board reference design featuring Altera Corporation's Stratix II FPGAs, along with their DDR2 SDRAM Megacore function memory controller, and Micron Technology, Inc.'s DDR2 SDRAM DIMM. Intellectual property (IP) from additional controller and memory suppliers will be added to the portfolio to create an environment in which systems designers can perform what-if analysis with multiple IC suppliers.
"Altera's contribution to the Allegro DDR2 design-in IP portfolio will accelerate the Stratix II design-in task," said James Smith, director of EDA partnerships at Altera. "Our IO models, reference design, and DDR2 layout guidelines captured in the Allegro constraint-management system allow our customers to optimize their DDR2 interconnect without compromising their schedule."
The design-in IP from Micron contains IO, package, and DIMM board models for their popular DDR2 devices. In addition, Micron has correlated the IBIS models with transistor-level models. The correlation study provides confidence to users of the design-in IP portfolio that DDR2 simulations with Allegro PCB SI are accurate and dependable.
"With the availability of the Allegro DDR2 design-in IP portfolio, our joint customers can efficiently design-in Micron DDR2 memory devices," said Jan Du Preez, vice president of Memory Marketing at Micron Technology, Inc. "As high-speed system designers increasingly design-in leading-edge memory devices, the DDR2 design-in IP portfolio for Allegro provides a methodology and reference material that enables first-time success."
The Cadence DDR2 design-in IP portfolio is available for download at www.cdnusers.org. More information on Cadence design-in IP portfolios is available at www.cadence.com.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.