Broadly Deployed OCP Verification Component Now Supports Mixed Languages
Pisa, Italy – October 2, 2006 - YOGITECH, the leading supplier of OCP based verification solutions, today introduced the industry’s first mixed-language OCP Universal Verification Component (UVC).
Supporting both e and SystemVerilog verification languages, the YOGITECH OCP UVC is the only commercial verification solution to fully support revision 2.1 of the OCP protocol and comply with the OCP 2.0/2.1 Compliant Checks document, including Functional Coverage Guidelines, released by the Open Core Protocol International Partnership (OCP-IP) earlier this year.
The OPC UVC is guaranteed to be tested and proven by means of an advanced qualification process addressing specific customers' profiles and with the same level of coverage both for e and SystemVerilog, allowing the final user to switch between the two languages at any time.
Built upon core technology used by leading semiconductor vendors for years in multiple designs, the YOGITECH OCP UVC combines the best of both worlds – a reliable silicon proven solution with state-of-the-art language support.
The OCP UVC is the only functional verification solution that can be adopted into any verification environment based on the standard languages endorsed by the IEEE, including SystemVerilog and ‘e’ verification languages, and SystemC, Verilog and VHDL design languages.
Users of YOGITECH verification components have consistently experienced significant reductions in the time to create sophisticated verification environments and regression suites.
More importantly, due to the coverage items provided by the verification components and the exhaustive built-in protocol checker , users isolate more design bugs sooner, including corner-case scenarios that would otherwise have made their way into silicon.
This level of dependable performance has saved users of YOGITECH verification components millions of dollars in development costs and has ensured products enter the market on time.
“We are pleased to be able to raise the value to customers of our OCP based offering extending our product portfolio with the OCP UVC.” said Silvano Motto, CEO of YOGITECH. “The combination of the YOGITECH OCP UVC and the Incisive Verification Platform is a golden solution to allow multi-language verification environments while maintaining the high level of verification productivity, predictability, and quality already achieved in the broadly deployed OCP eVC.”
“We are confident that the combination of the YOGITECH OCP UVC and the Incisive Verification Platform creates the industry’s most powerful OCP protocol verification environment.” said Steve Glaser, Corporate Vice President of the Cadence Verification Division. “We’re working closely with Verification Alliance Partners such as YOGITECH to deliver the next generation of multi-language universal verification components to bring our customers from plan to verification closure faster than ever."
For more information and a free evaluation of the YOGITECH OCP UVC, contact your regional YOGITECH sales representative.
YOGITECH is a company with proven experience in System-on-Chip (SoC) , Mixed-Signal design & verification, and fault-tolerant integrated circuits. Founded in 2000, YOGITECH leverages unique expertise in Specman Elite to provide sophisticated e and SystemVerilog Verification Components to the market.
A Sponsor Member of the OCP-IP consortium, YOGITECH is an active member of the Cadence OpenChoice Partnership and Verification Alliance.
YOGITECH is also a member of the SPIRIT Consortium and is an ARM Technology Access Partner.
YOGITECH offers a catalogue of eRM Verification Components to shorten time-to production of Intellectual Property cores and SoC designs based on standard protocols such as OCP, ATAPI, CAN and LIN.
Additionally, YOGITECH offers the Analogue Mixed-Signal Verification Kit (AMS vKit), a unique solution for the verification of mixed-signal circuits and systems.
Today, world leaders in the semiconductor industry rely on YOGITECH’s verification solutions and services.