EAST FISHKILL, NY -- October 03, 2006 -- IBM today announced new, low-power additions to its Power Architecture line of microprocessors and new processor cores that address the growing demand for high-performance processors that conserve energy.
In addition, the company expanded a university program designed to encourage development of broadband applications based on Power Architecture, which now accounts for a significant amount of all chip technology found in today's automobiles, supercomputers, network and communications equipment, printers and gaming consoles.
"Innovation in microprocessors is no longer about simply raising the bar on speed," said Ron Martino, director, Power Architecture Solutions, IBM Technology Collaboration Solutions. "IBM is committed to the development of high-performance, energy-efficient processors for a wide range of enterprise and consumer applications."
Two PowerPC processors now available
Specifically, IBM introduced two new off-the-shelf standard PowerPC single-core processors, both available immediately. The PowerPC 750CL, a 32-bit microprocessor, consumes half the energy as its predecessor, and performs at speeds ranging from 400MHz to 1GHz. The 750CL includes a 256KB L2 cache, and is targeted at networking, storage, imaging, consumer electronic and other high-performance embedded applications.
The PowerPC 970GX, a follow-on to the PowerPC 970FX, supports both 32-bit and 64-bit operations. It features the same power capabilities as its predecessor, but incorporates twice the integrated L2 cache at 1MB. The range of frequencies for the 970GX is 1.2 to 2.5GHz, enabling the chip to support high-bandwidth data processing and algorithmic intensive computations, making it suitable for communications, storage, multimedia and graphics based devices.
IBM also introduced the CPC965, a companion chip to the 970 series of processors designed to provide I/O connectivity and run at significantly less power than comparative bridge chips. The highly integrated CPC965 features a very high speed front bus that operates at up to half the processor frequency. Shipment of CPC965 samples is planned for March 2007.
IBM also announced three new 32-bit processor cores, including:
The 460S synthesizable core, which will allow designers to select the size L1 and L2 cache sizes and processor local bus (PLB) version necessary for implementing a single or cache coherent multi-processor design, and can be manufactured in any fabricator worldwide.
The 464FP H90, which is similar to the 464 H90 hard core, but with an integrated double precision floating point unit. Both application specific integrated circuit (ASIC) cores allow customers to more easily customize a chip design and have it manufactured with IBM or at Common Platform manufacturing facilities at Chartered Semiconductor Manufacturing and Samsung Electronics Co, Ltd.
Advances found within all three processor cores include:
- Low-power capability: The cores are high performance with virtually the same power requirements as their predecessors. The 464 H90 hard core is expected to dissipate slightly more than half a Watt (530mW) at 1GHz performance.
- Local bus connectivity: With IBM CoreConnect on-chip system architecture for easy support of system-on-chip (SoC) customizable designs.
- Application support: Designed for embedded applications including -- communications, network, aerospace and defense, consumer electronics, storage and printers.
Both PowerPC processors and the two ASIC hard cores are manufactured using IBM's 90 nanometer (nm) copper processing technology. The microprocessors also feature silicon-on-insulator (SOI) technology.
The 464 H90 hard core preliminary design kit is targeted for availability at the end of the year with the 464FP H90 preliminary design kit targeted in first quarter 2007. The planned availability of the 460S is second quarter 2007.
Empowering Universities Worldwide
Last December, IBM announced plans to make the specifications of the PowerPC 405 core available at no cost to the academic and research community The program was initiated in April to respond to requests by leading educators in computer science and participants in collaborative multi-core processing research projects who were looking to advance next-generation networking and communications devices, such as gaming consoles, mobile devise and consumer electronics.
Since then, 14 universities worldwide have joined the program and are leveraging the PowerPC 405 core. They are: Peking University, Saarland University, University of Maine, Shanghai Research Center for IC Design, University of Karlsuhe, Duke University, Harbin Institute of Technology, Stanford University, Yildiz Technical University, Helsinki University of Technology, Rice University, University of Illinois at Urbana-Champaign, Xi'an Jiaotong University and the University of Massachusetts at Amherst. In addition, Stanford University has signed the RAMP (Research Accelerator for Multiple Processors) license, giving them limited architecture rights for research purposes.
In other university-related news, Morgan State University recently received a grant from IBM to conduct teaching and research around Power Architecture technology. This semester, Power Architecture is being taught in three undergraduate courses in the department of electrical and computer engineering at Morgan State, located in Baltimore and designated as Maryland's public urban university.
IBM and EDA tool vendors plan to accelerate time to market
As development time and system-on-chip (SOC) complexity increase, the need to perform early design evaluation, parallel software development, simulation and co-verification increases. IBM recently signed agreements with leading EDA tool vendors Synopsys Inc., Mentor Graphics Corp., Summit Design Inc., CoWare Inc. and Poseidon Design Systems. CoWare will also be developing a processor support package for IBM's new PowerPC 750CL processor.
IBM is a founder member of Power.org, a community of more than 40 companies driving innovation around Power Architecture technology. Power.org provides an open ecosystem through which its members engage in collaborative innovation on Power Architecture technology. Power.org's mission is to optimize interoperability, accelerate innovation and drive increased adoption of this leading processor architecture. For more details, visit www.power.org
For more information about semiconductor technology at IBM, please visit: http://www.ibm.com/chips
PowerPC, IBM and the IBM logo are trademarks or registered trademarks of International Business Machines Corporation. Power Architecture and Power.org are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners.
"Wind River has been a long-time, strong supporter of IBM's Power Architecture and we are pleased to be able to offer full DSO platform support for the latest entry in IBM's product line, the 750CL. Wind River's real-time operating system, VxWorks, provides a small, scalable OS footprint, high reliability, high performance and real-time capabilities that match well to the IBM 750CL features. This combination makes an ideal fit for the advanced, resource-constrained devices of today's and tomorrow's markets." -- Warren Kurisu, director, Platform Product Management, Wind River.
"Marvell Discovery System Controller family is a market leader with multiple design wins across a broad spectrum of tier 1 customers. IBM and Marvell have a long history of delivering complimentary solutions that benefit our customers. IBM's new 750CL processor when combined with Marvell Discovery V system controller offers embedded system designers a high-performance, low power solution for cost sensitive applications." -- Viren Shah, director of marketing, Embedded and Emerging Products Business Unit, Marvell Technology.
"With DDR2 memory support and 2.5Watt typical power dissipation the Tundra Tsi109 is the ideal Host Bridge for power and cost sensitive applications. As shown on the evaluation platform, the Tundra Tsi109 together with the IBM750CL processor provides designers the ability to maximize performance at the lowest possible system cost and system power usage." -- Rick O'Connor, Chief Technology Officer, Tundra Semiconductor.