Advanced processor cores available by the end of this year enables highest quality video display on HD TVs and other video appliances
San Jose, California -- October 10th, 2006 -- Silicon Hive announced the HiveFlex VSP2100 Series of processor cores for video signal processing applications at the Micro Processor Forum’s 25th anniversary event in San Jose today, with a licensing program starting by the end of this year. The HiveFlex VSP2100 Series targets HD widescreen TVs with high quality video displays. The HiveFlex VSP 2100 series is built upon a tiled architecture with one tile offering 112 GOPS of 16 bit equivalent integer performance at 200 MHz, in a footprint of about 4 mm2 in a typical 65nm process. A tile is fully programmable and can support various video processing algorithms, including, codecs, de-interlacing, picture rate up-conversion, spatial scaling, etc., for displays up to HD (1920 x 1080) resolution. An entire video pipeline can be implemented with repeated use of the hardware tiles with different software running on each tile. TV and SoC manufacturers can now bring their products to market quickly, with the possibility of incorporating either, their own or even 3rd party algorithms in software.
The HiveFlex VSP2100 series of processor cores are delivered as synthesizable soft IP with a complete I/O subsystem for easy integration, and a full suite of test and verification tools. In addition the company sells the HiveGates VSP2100 Series FPGA based real time hardware emulation system for quick prototyping exercises. Ease of use has been maintained as with other HiveFlex processors by maintaining C programmability via Silicon Hive’s HiveCC™ compiler technology.
Geoff Burns, Silicon Hive’s Vice President of Product Management said, “Time is ripe for domain specific programmable solutions for high-performance video processing. The HiveFlex VSP2100 series caters to different market segments (mobile to HDTV). Not just video post processing for displays but also coding and decoding (H.264). This enables our customers to use one solution for the entire video pipeline which brings down SoC design time dramatically.”
The HiveFlex VSP2100 series is built upon a tiled architecture with each tile containing separate applications and vector compute engines and a programmable DMA engine. The compute engines perform a variety of scalar and vector operations in parallel. Each tile supports two levels of memory hierarchy level-1 (L1) and level-0 (L0). Video data planes, i.e. regions and windows of pixels, are stored in L1 and L0 memories. Because they support multiple video planes, L1 and L0 memories are content-aware. This hierarchical approach reduces the external memory access bandwidth requirements by up to a factor of 20 over traditional designs. Customers have the flexibility to choose several types of design time parameters, amongst others:
- Size of video region and window of interest (W.O.I.) per video plane
- Number of issue slots
- Choice of vector instructions and functional units per issue slot
- SIMD-factor (vector widths ranging from 4 – 128 ways)
- Number of bits per vector element (from 8 to 32)
- Number of words used in L0, L1, program, scalar, and vector memories
- Sizes of distributed register files
Silicon Hive will be demonstrating a working FPGA implementation of a HiveFlex VSP2100 series processor during the exhibition hours of the Fall 2006 Microprocessor Forum event in San Jose. About Silicon Hive
Silicon Hive is a worldwide supplier of semiconductor intellectual property. The company designs, builds and licenses application-specific solutions for communications and media processing; tuned processor cores; and program development tools with application libraries. Silicon Hive products enable semiconductor companies to make fully programmable System-on-Chips (SoCs). The patented technology has been matured over a 10-year period at Philips Research. Silicon Hive is a fully owned business of Royal Philips Electronics. More information on Silicon Hive is available at www.siliconhive.com