Aliso Viejo, CA -- October 11, 2006 -- Novelics, a memory IP provider for versatile and differentiated memory IPs, today announced its entry in the IP market with specific focus on providing low power memory blocks to be used by fabless semiconductor, SOCs, ASSP, and ASIC designers.
Founded in May 2005, Novelics comprises a team of seasoned engineering and management professionals whose backgrounds represent the convergence of three key areas: embedded memory volatile/non volatile memory (NVM) architectures, compiler design, and custom low power design. Novelics's management team has more than 60 man-years of combined industry experience. Moreover, Novelics’s track record of successful application for patents in their names as well as 9 additional patents-pending since founding Novelics, in conjunction with the depth and breadth of experience provided by the industry veterans on the company’s technical and business advisory boards further enhance the technical expertise of the team.
“Novelics was conceived with one primary purpose in mind,†said Cyrus Afghahi, Co-founder and CEO of Novelics. “Our mission is to revolutionize ‘cool’ embedded memory to achieve the best value for power, density, speed, reliability and cost. â€
“To enable fabless designers to break away from the trap created by huge cost add-ons for extra masks and lack of portability, an architectural breakthrough in design and automation was required. We have amassed an extraordinary team of engineers whose combined expertise in circuit design, modeling, compiler design, reliability, manufacturability, BIST/ BISR for repair, and low power architectures enable designers to implement their designs while they trade off power, density, reliability, performance, and cost,†said Afghahi.
“The coincidence of the potential to address convergence in the consumer space and create multi-million-gate designs with over 50% memory, which is today’s norm, is creating a plethora of explosive market opportunities,†said Farzad Zarrinfar, member of advisory board at Novelics. “The trick is to use MemQuestTM, the world’s first memory compiler for VM and NVM memory to perform tradeoff analysis and achieve design goals. We believe that customers would rather negotiate with a single supplier of differentiated IPs which is generated by MemQuest. Thus, wherever embedded memory finds their way into fabless designs, Novelics enables the designer to extract maximum performance with the least amount of design time, power dissipation, and cost.â€
Process and Technology Experience
Novelics has experience with over 10 different sub-micron processes including 0.25um, 0.18um, 0.13um, and 90nm feature processes. While other memory compilers have focused on developing generic least common-denominator libraries, Novelics’ memory design and MemQuest compiler take full advantage of custom design methodologies with the lowest power and highest performance and density in a given process. In addition to bulk CMOS logic process technologies, Novelics has experience with EEPROM, FLASH, and DRAM memory processes and design architectures.
EDA Tools & Interoperability
Novelics is interfacing very closely with leading EDA tool vendors to provide views that match all leading edge tools. Novelics has developed an interoperability and verification methodology to insure that highest quality for electrical, physical, simulation (Verilog & VHDL), and synthesis tools.
Management Experience
Dr. Afghahi received his Ph.D. from Linkoping University in Sweden and has 26 years of general management and technical leadership. Most recently Mr. Afghahi was technical director for the office of the CTO at Broadcom, a Principal Engineer at Intel, the head of the R&D group at Ericsson Radio, and Manager at SAAB electronic. He holds many patents and is the author of many articles
Dr. Terzioglu received his Ph.D. from Stanford University. He has over 7 years of principal engineering at Broadcom, and Micron Technology. He holds many patents and is the author of many articles.
Dr. Winograd received his Ph.D. from Stanford University. He previously served as Principal Engineer for 6 years at Broadcom. He holds many patents and is the author of many articles.
About Novelics
Novelics, headquartered in Aliso Viejo, California, supplies a portfolio of innovative embedded memory IPs for low power and high performance ASICs, ASSPs, and SOC designs. Our compiler-driven 'Cool' and 'zero-leakage' Memory IPs include OTP, SRAM-1T, SRAM-6T, high Speed Cache, and ROM.
These differentiated memory IPs are implemented with standard logic CMOS process with no additional masks or process steps to minimize cost, as well as maximize reliability and portability.
Our customers compete in low power consumer, industrial, wireless Applications, high speed computing and Networking. For more information, please visit www.novelics.com .