By Michael Santarini, EE Times
July 10, 2000 (10:42 a.m. EST)
Integrated Silicon Systems Ltd. (ISS; Belfast, Northern Ireland) has announced the first of a series of high-performance image and video compression application-specific virtual components. ASVCs, according to the company, are a form of licensable semiconductor intellectual property (IP) designed for easy implementation in submicron ASICs or high-density FPGAs.
The new 6100 family of products includes the CS6100 encoder, CS6150 decoder and CS6190 codec. Each product in the series is designed to accommodate continuous data flow (one image sample per clock cycle) and can be used in the most demanding frame-based video compression applications, without the need for host-processor intervention. The company claims the 6100 series is a fully comprehensive JPEG IP core solution.
The cores offer performance of up to 180 Msamples/second and many configuration options, and they support an unlimited range of image sources and color formats, ISS s aid. They are equally suited to battery-operated consumer electronics and professional video-editing and document-imaging equipment. The designs are fully synchronous and highly autonomous, offering automatic and manual configuration modes-and they don't require a coprocessor.
ISS's 6100 products also include a sophisticated bit rate control for bandwidth-limited applications and fully comply with ISO/IEC 10918-1/2 Baseline JPEG standards.
The CS6100 encoder compresses full-motion (30-frame/second), full-color video images up to 4 Mpixels. It sustains data rates over 180 Msamples/s and offers zero-power standby mode for portable applications.
For ASIC implementations, ISS offers the Optima series at $195,000 for a single-use license. For FPGA users, the Celerity series is priced at $65,000 for a single-use license. Optimized netlist versions for Optima and netlist versions of Celerity for Altera and Xilinx users are available directly from ISS or one of its agents.