Denali Software Inc. (Palo Alto, Calif.) has announced an online tool to generate memory subsystems. Its Databahn tool generates synthesizable memory controller cores for the latest memory architectures, and automatically produces C-level verification support for the memory controller and associated memory components.
Designers go online to select a set of memory components and specify a controller configuration. They instantly get synthesizable register-transfer level (RTL) code for the controller and C-level simulation models for the resulting memory subsystem, claims Denali, speeding system-on-chip design. Denali is targeting Databahn for technologies such as SDRAM, FCRAM and double-data-rate SDRAM, with plans to add support for other technologies later.
Databahn starts at $150,000, including a one-year subscription for online memory controller specification and model support for the controller and associated memory components. V isit (www.denalisoft.com) for details.
The first fruits of Xilinx Inc.'s deal to sell cores created by Integrated Silicon Systems Ltd. (ISS; Belfast, Northern Ireland) are out. The companies said that a 32-channel high-level data link controller, single-channel HDLC and 32-channel adaptive differential pulse-code-modulation (ADPCM) codec are available now.
Under the agreement, ISS multimedia and communications cores targeted for Xilinx FPGA architectures will be available for purchase as Xilinx LogiCore products (see June 26, page 56). They can be downloaded from the Xilinx Web site and optimized for Xilinx devices and design tools. The cores are designed to operate with the Virtex, Virtex-E, Spartan-II and future FPGA families.
The first three cores aim at accelerating the design cycle of high-density FPGAs in communications, targeting telecom applications such as Internet routers and switches and voice-over-Internet Proto col (VoIP) gateways.
The companies said the HDLC cores conform to the ITU Q.921 and X.25 recommendations for full-duplex, point-to-point and multipoint operation. They function at data rates of more than 40 Mbits/second and include a direct connection to PCM networks. These cores are suited for packet-switched data networks such as frame relay, broadband ISDN, T1/E1, T3/E3 and Sonet, as well as for packet-based digital subscriber line access multiplexers (DSLAMs).
The 32-channel ADPCM speech codec core, meanwhile, performs the ITU G.726 conversion of 64-kbit/s A-law or micro-law PCM channels to and from 40-, 32-, 24- or 16-kbit/s channels using the ADPCM transcoding technique. The core supports up to 32 duplex encoding/decoding channels or up to 64 encoding and/or decoding channels and can operate in burst or continuous mode. The codec targets applications such as central office DSLAMs, VoIP gateways, computer telephony, and DECT and wireless-local-loop phone systems where high-quality voic e compression is important.
The LogiCore products can be downloaded at (www.xilinx.com/ipcenter). Pricing is $7,200 for 32-channel HDLC, $3,900 for single-channel HDLC and $14,400 for 32-channel ADPCM cores.