Full eNB-IoT Release 14 IP solution with multi-constellation GNSS support for IoT devices
Standard eases IP tracking for royalty calculations
![]() |
Standard eases IP tracking for royalty calculations
By Michael Santarini, EE Times
June 26, 2000 (10:23 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000626S0008
The royalty model for silicon intellectual property recently received an ease-of-use-boost as the Virtual Socket Interface Alliance's Intellectual Property Protection Development Working Group (IPP DWG) released its Virtual Component Identification Physical Tagging Standard.
The standard will enable semiconductor foundries and virtual-component providers to track the use of cores and libraries through the fabrication process and to keep records on ownership and the numbers of components used. That should help foundries and virtual-component providers keep better accounting of per-chip royalties.
A tagging format, recorded in the standard GDSII-Stream file, provides complete virtual-component identification information and thus ensures a complete accounting and reporting of the intellectual property used. The VCID standard defines several criteria to ensure an accurate tagging process: required information, or standard definitions for the minimum information needed to ensure complete reporting; an encoding mechanism, which allows for arbitrary keywords and values; and a reporting mechanism, which allows a report for every virtual component on the chip to be produced from the required fields.
VCID is said to specify the coding of information necessary to track ownership of virtual components in any design. It also allows virtual-component users to label the components so foundries can run software that will identify such information as the virtual component's name, company and usage details. The document also defines operational programs to both write and read the information. The standard can tag all of the virtual components used in a single-chip design.
The VCID Standard (IPP 1 1.0) can be accessed and downloaded by VSIA members from www.vsia.org. Nonmember licenses are also available.
Related News
- DisplayPort Adds DockPort Extension to Royalty-Free VESA Standard
- Accellera Announces Standard for Tracking Soft Intellectual Property Usage through the Semiconductor Design and Development Process
- TSMC launches royalty-tracking system for IP cores in chips
- SoC-e networking IP porfolio extends with SpaceWire: The standard for Spacecraft communication networks
- Updated HBM Standard Geared for HPC, Networking
Breaking News
- UltraSoC extends on-chip analytics architecture for the age of machine learning, artificial intelligence and parallel computing
- Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES
- Can MIPS Leapfrog RISC-V?
- Soitec Becomes Strategic Partner of Silicon Catalyst Start-up Incubator
- Next-generation Armv8.1-M architecture: Delivering enhanced machine learning and signal processing for the smallest embedded devices
Most Popular
- Can Arm Survive RISC-V Challenge?
- Next-generation Armv8.1-M architecture: Delivering enhanced machine learning and signal processing for the smallest embedded devices
- Can MIPS Leapfrog RISC-V?
- Taiwan Maintains The Largest Share of Global IC Wafer Fab Capacity
- SMIC Reports 2018 Fourth Quarter Results
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |