XILINX RELEASES NEW HIGH PERFORMANCE
First products from OEM agreement with ISS include single-channel and 32-channel HDLC controllers plus ADPCM codec
SAN JOSE, Calif., June 26, 2000--Xilinx, Inc. (NASDAQ: XLNX) today announced the immediate availability of three high-level LogiCORETM IP products to accelerate the design cycle of high-density FPGAs in communications applications. The HDLC (high-level data link control) protocol controllers and ADPCM (adaptive differential pulse code modulation) codec cores are used in a number of telecom applications ranging from Internet routers and switches to VoIP gateways. The release of these Xilinx® LogiCORE products expands Xilinx leadership in system level solutions for the communications market.
"The Xilinx HDLC and ADPCM LogiCORE products address the exploding demand from telecom and network developers for complex Virtex-based IP for data and voice processing," said Babak Hedayati, director of marketing and business development for the Xilinx IP Solutions Division. "The HDLC and ADPCM protocols are two of the most popular methods to transmit data and voice over WAN systems. The availability of these cores on the Xilinx IP Center provides a one stop source to integrate telecom IP solutions into Xilinx FPGAs."
The HDLC cores conform to the ITU Q.921 and X.25 recommendations for full duplex, point-to-point and multi-point operation. The cores function at data rates over 40Mbits per second and include a direct connection to pulse code modulation (PCM) networks. The HDLC cores are ideal for public and private packet switched data networks such as frame relay switches, broadband ISDN, T1/E1, T3/E3, packet-based DSL access multiplexers (DSLAMs), remote/multi-service access concentrators and Sonet networks .
The 32-channel ADPCM speech codec performs the ITU G.726 conversion of 64 Kbits per second A-law or µ-law PCM channels to and from 40, 32, 24 or 16 Kbits per second channels using the ADPCM transcoding technique. The core supports up to 32 duplex encoding/decoding channels or up to 64 encoding and/or decoding channels and can operate in burst or continuous modes. It is real-time configurable for A-law or µ-law PCM encoding as well as various ADPCM compression rates including G.721 or G.723 mode operation. The ADPCM codec will be used in applications such as central office DSLAMs, VoIP gateways and access servers, computer telephony; and DECT and WLL phone systems where high quality voice compression is important.
The new cores operate with the Xilinx VirtexTM, Virtex-E, and Spartan®-II families of FPGAs. The new LogiCORE products are downloadable over the Internet from the Xilinx IP Center (www.xilinx.com/ipcenter), and used in conjunction with the Xilinx CORE Generator system to smoothly implement the cores into the Xilinx design flow. The three cores are the first products to result from a strategic partnership between Xilinx and industry leading IP developer Integrated Silicon Systems Ltd. (ISS).
License price and availability
The HDLC and ADPCM cores are available now. Pricing for the cores are $7,200 for 32-channel HDLC, $3,900 for single-channel HDLC, and $14,400 for 32-channel ADPCM. Licensing information and instructions for downloading the cores and information on all Xilinx LogiCORE products can be found at the Xilinx IP Center.
Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com