SAN MATEO, Calif. Cadence Design Systems Inc. has introduced the Transistor Logic Abstracter (TLA), which generates logic-level Verilog functional models from Spice or Spectre transistor-level netlists. The models can then be used for logic-level verification in gate-level simulation, emulation and formal equivalence-checking tools.
The tool is targeted at speeding up the verification process for full-custom designers, said Erich Marschner, architect and acting product marketing manager for TLA at Cadence (San Jose, Calif.).
Up to now, said Marschner, full-custom designers had to rely on painfully slow but accurate Spice simulators or else use less accurate pattern-matching tools for moving models to the gate level. The new tool allows full-custom designers to generate Verilog from Spice and then, among other things, check logic model equivalency to register-transfer-level models for faster verificati on.
"One of the reasons behind our development of TLA is that we realized while working on equivalence checking that one of the major areas where equivalence checking was needed is in the custom-design area," said Marschner. "We saw with TLA the opportunity to extend logic-level functional equivalence checking into the custom arena."
Alok Jain, the tool's lead architect at Cadence, said traditional tools in this area are targeted mainly for structured-custom and semicustom designers and require users to break the design into blocks and then run pattern matching. The pattern-matching tools, however, do not account for interaction between blocks and also require users to maintain large pattern databases, said Jain.
In contrast, the TLA tool uses a new analytical technique Jain developed during his master's work at Carnegie Mellon University.
Jain said the TLA focuses on timing-independent functionality and MOS transistor digital design and is able to abstract the most complex functional blocks, including content-addressable memories, RAMs and ROMs.
Jain said the tool's use of analytical techniques ensures that its output is functionally correct, and enables it to handle both combinational and sequential circuits implemented in any of the common digital MOS design styles. Those include static CMOS, ratioed logic, precharge/domino logic, pass-transistor logic and cascode voltage-switch logic.
Jain said that if a design does have timing-dependent functionality, engineers can "black box" those sections and use TLA to create a Verilog functional model for the rest.
The TLA, running on Sun and HP workstations, starts at $72,000.